Sample and hold circuit
AssigneeSony Corporation
InventorFumio Ishikawa
Life of this patent
Estimating the term…
Abstract
A sample and hold circuit is disclosed, in which first and second terminals to which are supplied drive currents for turning ON and OFF a diode bridge are respectively connected through capacitors to a connection point between output electrodes of switching elements, a diode is connected between the first and second terminals for short-circuiting the capacitors when the diode bridge is made OFF, and input electrodes of the switching elements are respectively connected to first and second points of a reference potential whereby said diode bridge is made ON by a drive current flowing from the first point to the second point of the reference potential.
Claims11
An integrated sample and hold circuit of the bridge type, comprising:
- a diode bridge, having an input terminal and an output terminal;
- first and second drive terminals on said bridge;
- first and second capacitors coupled to said first and second drive terminals respectively;
- first switching means having first and second states coupled between said first and second capacitors;
- second and third switching means for producing two control signals of opposite phase at respective outputs in response to input switching pulse signals of opposite phase;
- said output of said second and third switching means connected respectively to said first and second capacitors in series with said first and second drive terminals, respectively, for applying said control signals to said capacitors for turning said bridge ON and OFF;
- said first switching means being in said first state when said bridge is turned OFF and being in said second state when said bridge is turned ON;
- said capacitors establishing the voltage at both said drive terminals at a voltage equal to the voltage appearing at said input terminal in response to said first state of said first switching means;
- and
- said first capacitor establishing the voltage at said first drive terminal at a voltage equal to said input voltage plus a predetermined offset voltage and said second capacitor establishing the voltage at said second drive terminal at a voltage equal to said input voltage minus said predetermined offset voltage in response to said second state of said first switching means.
Dependencies are inferred from the claim text.