Static-type semiconductor memory device
AssigneeFujitsu Limited
InventorAtushi Oritani
Life of this patent
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Abstract
In a static-type semiconductor memory device, one word line (WL.sub.0, ---) and one pair of bit lines (BL.sub.0, BL.sub.0, ---) are selected by row address decoders, column address decoders, and the like, upon receipt of address information so as to select one memory cell (C.sub.00, ---). The row address decoders are activated by a word-line driver clock signal (.phi..sub.W) of a word line driver. The word-line driver clock signal (.phi..sub.W) is generated only during a predetermined time period after the change of address information, and, accordingly, the selection time period of the word line is small.
Claims7
A static-type semiconductor memory device operatively connectable to receive row address and column-address information signals, comprising:
- first and second power supply terminals;
- a plurality of word lines;
- a plurality of pairs of bit lines intersecting said plurality of word lines;
- a plurality of load means, each of said plurality of load means operatively connected to one of said bit lines and to said first power supply terminal, for charging said plurality of pairs of bit lines;
- a plurality of static memory cells, each of said plurality of static memory cells operatively connected to one of said word lines and to one of said pairs of bit lines;
- row-addressing means, operatively connected to said word lines and operatively connected to receive the row-address information signals, for selecting one of said word lines upon receipt of the row-address information signals;
- column-addressing means, operatively connected to said plurality of bit line pairs and operatively connected to recive the column address information signals, for selecting one of said bit line pairs upon receipt of the column-address information signals;
- a sense amplifier, operatively connected to said plurality of bit lines, for amplifying the difference in potential between a pair of bit lines selected by said column-address means and providing an output potential;
- an output buffer, operatively connected to said sense amplifier, for maintaining and outputting a data output signal;
- a word driver, operatively connected to said row-addressing means, for activating said row-addressing means;
- a first clock signal-generating circuit, operatively connected to said word driver, for detecting the change of said row-address information signals and said column-address information signals and generating a first clock signal, the rise of said first clock signal setting said word driver;
- and
- a second clock signal-generating circuit, operatively connected to said plurality of word lines and said word driver, for detecting the change of the potential of said word lines and generating a second clock signal, the rise of said second clock signal resetting said word driver.
Dependencies are inferred from the claim text.