Semiconductor memory
AssigneeHitachi, Ltd.
InventorsKatsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Abstract
A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
Claims1
A semiconductor memory comprising:
- a plurality of pairs of data lines;
- differential amplifiers, each of which amplifies a difference between signal levels appearing on each pair of data lines;
- word lines, each of which is arranged so as to intersect with each pair of data lines;
- and
- precharging circuits, each of which sets each pair of data lines at a potential intermediate between binary signal levels to be stored in memory cells, before operation of the corresponding differential amplifier is started.
Dependencies are inferred from the claim text.