Method and apparatus for handling interprocessor calls in a multiprocessor system

A multiprocessor system for executing a plurality of program processes each process having an associated program function context, comprising:

• a plurality of processors;
• storage means for storing an indication of the identity of a designated one of said plurality of processors and of a first program function and for storing said program function contexts;
• bus means for accessing said storage means;
• each of said plurality of processors comprising means for accessing said program function contexts in said storage means via said bus means and each operative under program control to initiate a process;
• work queue means associated with each of said processors;
• said processors operative under program control to store a link to a predetermined program function context and to said first program function in the work queue means associated with said designated processor;
• wherein said designated processor is operative to execute said first program function using said predetermined program function context.

A multiprocessing system for executing a plurality of program processes, comprising:

• a plurality of processors, each of said processors comprising local memory means;
• storage means for storing data words;
• bus means interconnecting said processors and said storage means;
• said processors comprising means for transmitting to said bus means words representing a first address and a processor identification, a first length of a block of data and said processor identification, and words representing each of a first series of data words each with said processor identification, and words representing a second address and said processor identification and a second length of a block of data and said processor identification, and for receiving from said bus means words representing each of a second series of data words, each with said processor identification, corresponding to said second address and length;
• said storage means comprising means for receiving from said bus means words representing said first address and said processor identification, said first length of a block of data and said processor identification, and words representing each of said first series of data words each with said processor identification, and words representing said second address and said processor identification, and said second length of a block of data and said processor identification, and are responsive to words representing said second address and said second length of a block to transmit on said bus means words representing each of a series of data words each with said processor identification, whereby the consecutive data words for a number of transactions from and to different processors can be interleaved on the bus and can be identified by said processor identification.

A data processing system comprising:

• processor means for generating virtual address signals and first physical address signals said virtual and physical addresses occupying different address ranges;
• a memory module;
• and
• address translation means for recognizing said virtual address signals and responsive to said virtual address signals to generate and transmit corresponding second physical address signals to said memory module and for recognizing first physical address signals and transmitting said first physical address signals without translation to said memory module;
• wherein said address translation means comprises a plurality of serially interconnected translator blocks for generating translator data, each of said translator blocks comprising memory means and register means, and adder means for adding the contents of said memory means and said register means to generate memory addresses for the next block, said plurality of blocks comprising:
• a first block responsive to said virtual addresses to generate first intermediate translator data, and a last block responsive to intermediate translator data from the preceding block to generate physical addresses.

In a multiprocessing system having a plurality of processors for executing a plurality of program processes, said system comprising shared memory means, bus means connected to each of said processors and each of said shared memory means, a method of transferring a block of data between any of said processors and any of said shared memory means comprising the steps of:

• transmitting a starting address, a read/write transfer command and an identification of one of said processors from said one of said processors to one of said shared memory means;
• transmitting data specifying a length of a block of data and said identification from said one of said processors to said one of said shared memory means;
• transmitting a block of data corresponding to said length from said one of said processors to said one of said shared memory means and transmitting said identification with each word of said block in case a write transfer command has been sent;
• and
• transmitting a block of data corresponding to said length from said one of said shared memory means to said one of said processors and transmitting said identification with each word of said block in case a read transfer command has been sent.

In a multiprocessing system having a plurality of processors each of the processors having an associated work queue, comprising storage accessed by virtual addressing and a translation table specifying virtual to physical address mapping, the method of executing a program process having an associated program function context, stored in memory accessible by each of said processors, by different processors, comprising the steps of:

• initiating a process comprising a first and a second function in any of said plurality of processors;
• storing an indication of the physical identity of a first processor and an indication of the address of a first function in said translation table;
• executing said second function by means of a second processor said executing step including the step of entering data into said associated program function context stored in memory accessible by each of said processors;
• storing a link to said associated program function context and said indication of the address of said first function in the work queue associated with said first processor;
• and
• executing said first function by means of said first processor using said program function context containing said data entered into said program function context during execution of said second function, whereby said first program function executed by means of said first processor is linked to said second program function executed by said second processor and uses said program function context containing data entered during execution of said second function.

A multiprocessor system for executing a plurality of program processes each process having an associated program function context stored in memory, comprising:

• bus means;
• storage means accessed by virtual address signals via said bus means for storing said program function contexts;
• a plurality of processors connected to said external bus means for accessing data in any of said program function contexts;
• work queue means associated with each of said processors;
• address translation mens to translate from virtual addresses to physical addresses;
• said address translation means operative to store table data specifying the identity of a processor designated to execute a first program function and specifying an indication of the address of said first program function;
• said system operative under program control to store a link to a predetermined program function context and said indication of the address of said first program function in the work queue means associated with said designated processor;
• and
• said designated processor further operative to execute said first program function linked to the queue means associated with said designated processor and further specified by said predetermined program function context.

In a multiprocessor system using virtual addressing, an address translator connectable to a source of virtual address signals for translating from initial input signals comprising a virtual address signal to a final output signal comprising a physical address signal, comprising:

• a first block, responsive to said initial input signals and comprising a first input register responsive to a preselected portion of said initial input signals and adapted to generate a first register output signal and a first portion signal corresponding to the contents of a first predetermined portion of said first input register, a first random access memory responsive to a second preselected portion of said initial input signals to generate a first memory output signal, and a first adder means responsive to said first portion signal and said first memory output signal to generate a first sum signal;
• a second block comprising a second input register responsive to said first register output signal and adapted to generate a second register output signal and a second portion signal corresponding to the contents of a second predetermined portion of said second input register, a second random access memory responsive to said first sum signal to generate a second memory output signal, and a second adder means responsive to said second portion signal and said second memory output signal to generate a second sum signal;
• a third block comprising a third input register responsive to said second register output signal and adapted to generate a third portion signal corresponding to the contents of a third predetermined portion of said third input register, a third random access memory responsive to said second sum signal to generate a third memory output signal, and a third adder means responsive to said third portion signal and said third memory output signal to generate said final output signal comprising the physical address signal corresponding to said virtual address signal;
• in which said first, second and third blocks are operative to work on translations of different virtual address signals at any one time;
• whereby translation actions are pipelined.