US 4,539,564 A · Electronically controlled interconnection system

Abstract

An all electronic interconnect system having high flexibility, low cost, and higher reliability. A central matrix is formed from a multiplicity of solid state analog switches in which each switch is controlled by a digital address. Each switch can connect a common switch point to one of a multiplicity of outputs. For use with digital devices such as computers and peripherals, a multiplicity of rows of the matrix may be connected to accept an N-bit parallel byte and to output such an input selectively to one of several channels. The channel to which the input is connected is selected by a digital address to each of the analog switches in the row. By using a multiplicity of rows, the matrix is built up to interconnect a number of input digital devices to a number of output devices through control of the electronic addresses. Control circuits are provided which permit rapid interconnection of any input device to any output device. A maintenance channel system is included which permits real time monitoring of the input and output of any digital connection to quickly locate sources of errors. The use of analog switches in the matrix eliminates the need for synchronization of the digital information and also permits the system to interconnect analog devices.

Claims13

Dependent claims

A four-wire duplex interconnection system for selectively connecting M pairs of digital data sources and sinks simultaneously to N pairs of digital data sources and sinks in which said digital data is composed of parallel bytes of X digital bits comprising:

an interconnection matrix having M rows and X columns, each of said M rows serving as an input port for one of said M pairs of data sources and sinks;
a plurality of analog switches, a pair of said switches disposed at each intersection of said rows and columns, each of said switches having a common input and X poles, and a digital address input for receiving a different digital address associated with each of said poles, said poles having a common input selectably connectable to one of said poles in response to its digital address, each of said common inputs serving as an input port for one of said X bits from or to a source or sink connected to said port wherein respective ones of said X poles of each pair of said switches in one of said rows are connected in parallel with the respective ones of said X poles of each pair of said switches in all other of said columns;
X output busses, each of said busses having 2X conductors, each of said busses formed by a conductor from one pole of each of said switches in each column of said paralleled switches, said busses providing output connections to said N pairs of data sources and sinks;
and
channel selection means for generating X addresses indicative of each of said X output busses, said channel selection means having a separately controllable address output connected to each of said rows of said switches whereby said M pairs of sources and sinks are connectable, selectively to said N pairs of data sources and sinks.

2 more elements

An interconnection system for selectively connecting M digital data sources generating parallel bytes of n bits with parallel digital data sinks comprising:

(a) an interconnection matrix having n columns and m rows, each of said m rows serving as an n terminal input port for receiving said parallel digital data bytes thereby providing m ports and said n columns serving as a set of N output channels for connection to a set of data sinks;
(b) a multiplicity of analog switches, at least one of said switches disposed at each intersection of said columns and rows, each of said switches having
(i) n outputs with each output serving as a lead for one of said n bits, each of the corresponding n outputs of all switches in a column connected in parallel;
(ii) a common input selectively switchable to establish an analog path to any one of said n outputs, each of said common inputs in a row serving as an input port terminal for one of said n bits from a data source;
and
(iii) an address input for electronically switching said common input to any one of said n outputs, said address inputs for all switches in each one of said rows connected in parallel;
whereby said N output channels are produced by forming N busses from the like numbered outputs of each set of said analog switches in said n columns;
and
(c) channel selection means for generating addresses indicative of each of said N channels, said channel selection means connected to said address input for each of said m rows, said channel selection means controllable to thereby connect any of said N channels to any one of said M ports.

6 more elements

Dependencies are inferred from the claim text.

Electronically controlled interconnection system

Life of this patent

Electronically controlled interconnection system

Life of this patent

Abstract

Claims13