Prioritized clock selection circuit

A clock selection circuit for use in a switching system which includes a plurality of clock circuits, each being operative to provide a stream of clock pulses, said clock selection circuit comprising:

• a plurality of delay circuits each connected to all but one associated clock circuit and each being operative to provide a time-out signal;
• a plurality of clock pulse detection circuits, each connected to said associated clock circuit and operative, in response to an absence of a clock pulse for a predetermined time, to provide a clock failure signal;
• a plurality of storage circuits each connected to a different one of said delay circuits and a different one of said detection circuits, and each being operative in response to the time-out signal from the connected delay circuit to provide a clock enable signal for said associated clock circuit, and each of said storage circuits being further operative in response to the clock failure signal from the connected clock pulse detection circuit to provide a clock disable signal for said associated clock circuit;
• and
• a clock signal gating circuit connected to said plurality of clock circuits and said plurality of storage circuits and operative in response to each of said clock enable signal to gate clock pulses from the associated clock circuit to said switching system;
• each of said delay circuits being operative in response to simultaneous presence of said clock disable signal from all of the unassociated clock circuits to provide said time-out signal after a different predetermined time.