Nonvolatile memory cell

A nonvolatile static semiconductor random access memory cell for use in array of cells comprising:

• means to generate a store signal if the power to said cell is interrupted;
• a bistable circuit operable to maintain a first state when switched to said first state and operable to maintain a second state when switched to said second state;
• floating gate means operable to maintain a first negatively charged condition in response to said store signal if said bistable circuit is in one of said states and a second uncharged condition if said bistable circuit is in the other state, said first and second conditions being maintained when outside power is interrupted;
• disabling means connected to prevent said bistable circuit from assuming said first state, when power is restored, if said floating gate means is in said first condition;
• and
• reset means operable to set said bistable circuit to said first state upon restoration of power unless said disabling means prevents reset
• wherein said bistable circuit comprises first, second, and third nodes, a first FET connected between said first node and the array supply voltage with its gate connected to said second node, a second FET connected between said second and third nodes with its gate connected to said first node, a variable voltage supply connected to said third node, said bistable circuit being switched to said first and second states by the application of first and second voltages respectively to said first node.