Enabling circuit for redundant word lines in a semiconductor memory array

#The present invention relates to peripheral circuits for use with semiconductor memories employing MOS storage devices arranged in primary and redundant array configuration and is more particularly directed to a circuit which enables the redundant word lines in the redundant array for the purpose of providing back-up storage capacity should any of the storage devices in the primary array fail.

#The use of MOS floating gate storage devices in semiconductor memories has increased rapidly in recent years. A typical MOS floating gate storage device includes a floating gate structure disposed over the surface of a semiconductor substrate between spaced-apart source and drain regions. A control gate is then vertically aligned with the floating gate. In order to program the storage device, a potential is applied to the control gate such that charge carriers are transported between the semiconductor substrate and the floating gate, whereupon the threshold voltage in the channel region established between the spaced-apart source and drain regions is modified. During read operations, the presence or absence of charge carriers on the floating gate can be determined by simply measuring the presence or absence of current flow through the channel region in response to voltage potentials applied to the drain region. When floating gate storage devices of the type described above are incorporated in a semiconductor memory array, individual floating gates are utilized for each storage device while a single conductive strip is generally etched to define the control gates for all of the storage devices in a single memory array row. This single conductive strip is commonly known as a word line. The memory array is prepared for programming or read operations by enabling the word line of a particular memory array row using a unique x-address applied to the address inputs of the memory array. During manufacture of the memory array, defects in various storage devices positioned along one or more rows in the memory array may occur, giving rise to erroneous data read-outs when the word line connected to the defective storage devices are addressed. In order to salvage memory arrays having such faulty word lines, semiconductor manufacturers often construct memory arrays with several additional or redundant rows of storage devices, each redundant row being tied to a redundant word line. If a faulty word line is located during quality control examination of the memory array, the x-address of the faulty word line is programmed into an enabling circuit for one of the redundant word lines. Thereafter, whenever the faulty word line is addressed, the redundant word line will instead be enabled. It can thus be seen that the presence of redundant word lines in a semiconductor memory array significantly increases the manufacturing yield from any batch of memory arrays undergoing simultaneous construction. Despite the advantages inherent in increased manufacturing yields, however, prior art redundant row techniques do not provide any means for determining whether the redundant word lines of a given memory array have, in fact, been programmed for use. Hence, the provision of a means for ascertaining the status of any redundant word lines employed in a semiconductor memory array would be of obvious benefit.

#It is accordingly an object of the present invention to construct a semiconductor memory having back-up storage devices arranged along redundant word lines for the purpose of providing back-up storage capacity, the semiconductor memory also including means for enabling the redundant word lines in response to a selected x-address and means for generating a signal indicative of redundant word line use.

#The various features, objects and advantages of the present invention will become more apparent upon consideration of the following Brief Description of the Drawings and Best Mode for Carrying Out the Invention, wherein:

#FIG. 1 is a schematic representation of a semiconductor memory comprising floating gate storage devices arranged along primary and redundant word lines to form primary and redundant arrays;

#FIG. 2 is a circuit diagram of a dual-function address buffer capable of generating control signals for use in the redundancy decoder and redundancy disable circuit of the present invention;

#FIG. 1 schematically illustrates a semiconductor memory having a plurality of MOS storage devices 4 arranged to form a primary array 6. Each of the storage devices 4 comprises an electrically-programmable read-only floating gate structure of the type disclosed in U.S. Pat. No. 4,075,045. A series of bit lines 8 arranged in columns and primary word lines 10 arranged in rows are respectively connected to the storage device drains 12 and control gates 14, whereby each storage device may be individually programmed and read in accordance with a unique storage device address. Specifically, primary word lines 10 serve to define the x-addresses of the storage devices while bit lines 8 serve to define the storage device y-addresses. Thus, in 64k-bit embodiment, memory 2 includes two hundred and fifty-six primary word lines designated X.sub.1, X.sub.2. . . X.sub.256 and two hundred and fifty-six bit lines designated Y.sub.1, Y.sub.2. . . Y.sub.256. If desired, the bit lines can be subdivided into eight groups of 32 bit lines each to enable the simultaneous storage of an 8-data bit word, i.e., a data byte, using only a single y-address. In the latter event, each of the eight bit lines activated by the single y-address may be arranged in interleaved fashion.

#Programming or reading of a particular storage device, or set of storage devices where bit lines 8 are divided into interleaved groups, is initiated by applying a digital address signal A.sub.0, A.sub.1. . . A.sub.n to a series of address bit inputs 16. In the 64k-bit embodiment of memory 2 described above, the first five address bits A.sub.0 -A.sub.4 establish the particular y-address Y.sub.1, Y.sub.2. . . Y.sub.32 of each data byte while an additional eight address bits A.sub.5 -A.sub.12 establish the data byte x-address X.sub.1, X.sub.2. . . X.sub.256. Address bit inputs 16 respectively feed the address bits A.sub.0 -A.sub.12 to a series of address buffers 18. Each of the address buffers in turn generates an address indicator AI.sub.i and an inverted address indicator AI.sub.i, for use in decoding the address signal. That is, the output of the address buffers 18 which receive address bits A.sub.0 -A.sub.4 comprise a series of address indicators AI.sub.0 -AI.sub.4 and inverted address indicators AI.sub.0 -AI.sub.4, whereas the output of the address buffers 18 which receive address bits A.sub.5 -A.sub.12 comprise a series of address indicators AI.sub.5 -AI.sub.12 and inverted address indicators AI.sub.5 -AI.sub.12. Address indicators AI.sub.5 -AI.sub.12 and inverted address indicators AI.sub.5 -AI.sub.12 are supplied to X-decoders schematically illustrated at 20 and are combined in a digital logic system to enable the specific primary word line 10 associated with the x-address established by address bits A.sub.5 -A.sub.12. Simultaneously, the address indicators AI.sub.0 -AI.sub.4 and inverted address indicators AI.sub.0 -AI.sub.4 are supplied to Y-decoders illustrated schematically at 22. The Y-decoders operate in conjunction with a column decoder 24, combining the various address and inverted address indicators in a digital logic system such that selected bit lines 8 associated with the y-address established by data bits A.sub.0 -A.sub.4 are enabled. Data is then programmed into or read out of primary array 6 by connecting each enabled bit line 8 to the appropriate one of a pair of input/output buffers 26 respectively tied to output pads 28 and then entering or reading out the appropriate data bit O.sub.0 -O.sub.7. As further disclosed in co-pending application Ser. No. 346,159 filed Feb. 5th, 1982 and incorporated herein by reference, the time required to program individual storage devices 4 in primary array 6 can be significantly reduced by increasing the programming voltage present on the primary word lines 10 associated with the individual storage devices 4. To this end, a series of word line charge pumps 30 driven by a high voltage oscillator 31 are respectively connected to primary word lines 10 in order to raise the voltages thereof to a predetermined level during memory programming operations.

#Memory 2 is additionally provided with a redundant array 32 of storage devices 4 arranged along redundant word lines 34 for the purpose of providing back-up storage capacity should any of the primary word lines 10 in primary array 6 prove faulty, i.e., should any of the storage devices 4 associated with primary word lines 10 contain manufacturing defects. The redundant word lines 34 are connected to the control gates 14 of storage devices 4 to establish alternate x-addresses for the memory. When a faulty word line is present at a particular x-address in primary array 6, address indicators AI.sub.5 -AI.sub.12 and inverted address indicators AI.sub.5 -AI.sub.12 generated by address buffers 18 as a function of the address bits A.sub.5 -A.sub.12 corresponding to the x-address of the faulty primary word line are used to program a redundancy decoder 36 such that any subsequent address signal A.sub.0 -A.sub.12 having the x-address of the faulty word line in primary array 6 will instead enable a selected redundant word line 34 in redundant array 32. A series of control signals supplied to redundancy select lines 37 via the output pads 28 associated with data bits O.sub.0 -O.sub.3 are gated through a set of redundancy enable transistors 38 to assist in programming redundancy decoder 36. Once a particular x-address has been transferred from primary array 6 to redundant array 32, a redundancy disable circuit 39 prevents any accidental reprogramming of redundancy decoder 36 relative to the selected redundant word line 34 enabled by the particular x-address. The redundancy disable circuit additionally generates a redundancy disable signal RD.sub.1 -RD.sub.4 indicative of the fact that the selected redundant word line is in use, which redundancy disable signal can be supplied back through redundancy enable transistors 38 to an appropriate output pad 28.