High frequency generator with output shut-off or reduced by biasing multiplier diode

#This invention relates to a device for generating high frequency signals such as microwave or milliwave signals and particularly to a method of controlling an output of a high frequency generator, including miltiplier means, having diodes, within the output of the generator.

#High frequency generators, generators used for obtaining predetermined frequency signals by multiplying the outputs from a high frequency oscillator comprising a frequency stabilizing circuit such as Phase Lock Loop (PLL), are known. The high frequency generating means is required to turn the output off for a while after the power switch is turned on, because an abnormal frequency may be generated up until the frequency stabilization reaches a steady state due to the operation of a frequency stabilizing circuit.

#The output of a high frequency generating means is turned off by the following methods: first, an ON/OFF circuit, such as diode switch using a PIN diode or coaxial relay, is inserted into the output and second, an output is turned off through suspension of operation by changing the bias of an amplifier used in the output circuit. The former method has a disadvantage in that the circuit structure is complicated because an ON/OFF circuit is added and moreover signal loss therein is inevitable. The latter method cannot be applied in a device not having an amplifier. In both of these methods, the output is turned off in the output frequency stage and shielding must be taken into account in order to obtain a large attenuation of the output, resulting in an increase in the device cost.

#FIG. 1 is a block diagram of an embodiment of a high frequency generator of the invention;

#FIG. 2 is a schematic diagram of the multiplier means 6 of FIG. 1;

#FIG. 3 is a schematic diagram of a second embodiment of the multiplier means 6 of FIG. 1;

#FIG. 1 is an embodiment of a high frequency generator of the invention. In FIG. 1, 1 is a voltage controlled oscillator (referred to hereinafter as a VCO). An output of the VCO 1 is applied to a harmonic mixer 2 and is compared with a reference frequency input signal from terminal 3. An error signal output of the harmonic mixer 2 is fed back to the VCO 1 through a loop filter 4, thus forming a phase lock loop (referred to hereinafter as a PLL). An output of the VCO 1 is applied to a multiplier means 6 via a circulator 5, forming an isolator, and is multiplied to provide a high frequency output to the output terminal 7. A monitoring circuit 8 monitors the synchronization of the PLL depending on the output of the loop filter 4. When the detected output of the monitoring circuit becomes OFF, a bias controlling means 11 generates a specified control voltage and the voltage is applied to the multiplier means 6. Thus, the high frequency output of the multiplier means 6 becomes OFF.

#The PLL circuit comprising the VCO 1, harmonic mixer 2 and loop filter 4, is already known. The oscillation frequency f.sub.o of the VCO 1 is controlled by a signal applied thereto via the loop filter 4. However, since the reference frequency input signal, f.sub.R =f.sub.o /n.sub.1, having a high frequency stability and generated by a crystal oscillator etc., is applied to the terminal 3, the harmonic mixer 2 compares the phases between the harmonic f.sub.o which is n.sub.1 times the reference frequency signal and an output signal f.sub.o of the VCO 1 and generates an error signal output. The error signal output of the harmonic mixer 2 passes the loop filter 4 and is fed back to the VCO 1 as a high frequency control voltage. Accordingly, control is carried out in the PLL circuit so that the error signal output from the harmonic mixer 2 is close to zero, thereby stabilizing the oscillation frequency of the VCO 1.

#An oscillation output signal of the VCO 1 is input to the multiplier means 6 via the circulator 5. The circulator 5 is provided to reduce the load effect on the multiplier means 6 When the input frequency f.sub.0 is about 2 GHz, the multiplier means 6 uses a step recovery diode (referred to hereinafter as a SRD) as a semiconductor element and is capable of obtaining the multiplication steps n.sub.2 =4, etc.