Clock extraction circuit using an oscillator and phase-locked programmable divider

Abstract

The present invention is a phase-locked circuit for use in digital circuits such as a high frequency clock generator, counter and memory. The circuit provides an output which is locked to the received input tone signal in both frequency and phase. The circuit includes an oscillator for generating a clock signal having a frequency higher than the frequency of an input signal; a phase information extractor for extracting phase information corresponding to the period of the input signal and forming a pulse train based on the phase information; an average period count/storage circuit for measuring an available period of input signal by counting the number of pulses of said clock signal during an interval of a predetermined number of input periods obtained by counting pulses of the pulse train based on said phase information and storing the count; a programmable counter for dividing the frequency of said clock signal in accordance with the stored count and providing an output signal; and a phase comparison/correction means for comparing said output signal with the phase information of said input signal, and producing a phase correction signal as a result of said comparison; whereby said programmable counter increases or decreases said stored count in accordance with said phase correction signal to modify the phase of said output signal.

Dependencies are inferred from the claim text.