JFET Differential amplifier stage with method for controlling input current

A JFET (junction field effect transistor) differential amplifer stage, comprising:

• first and second JFETs connected in a differential amplifier stage with their sources connected together, and their gates adapted to receive respective input voltage signals,
• a current source connected to supply current to the JFETs, the magnitude of current supplied by said current source being great enough to establish gate-source voltages for the two JFETs which are less than their pinchoff voltages (V.sub.p),
• a third JFET cascoded with the first JFET and with its gate connected in circuit with the source of the first JFET,
• a fourth JFET cascoded with the second JFET and with its gate connected in circuit with the source of the second JFET,
• the third and fourth JFETs being matched with the first and second JFETs and each developing a voltage at least as great as the differential between the gate-source voltage and V.sub.p for their respective first and second JFETs, whereby the gate-drain voltages of the first and second JFETs are maintained at at least V.sub.p to keep them in a saturated mode with a high output impedance.

A JFET (junction field effect transistor) differential amplifier stage characterized by a low input bias current, comprising:

• first and second JFETs connected in a differential amplifier stage with their sources connected together and their gates adapted to receive respective input voltage signals,
• third and fourth JFETs cascoded respectively with the first and second JFETs, the gates of the third and fourth JFETs connected respectively in circuit with and at substantially the same potential as the sources of the first and second JFETs, and their drains providing output currents,
• a current source connected to supply source current to the cascoded JFETs in an amount which is no greater than 0.25I.sub.DSS for each JFET, thereby establishing a gate-source voltage for each JFET which is at least as great as 0.5V.sub.p, and accordingly a gate-drain voltage for the first and second JFETs which is at least as great as V.sub.p for those JFETs, whereby the first and second JFETs are kept in a saturated mode with a high output impedance, and
• fifth and sixth JFETs connected to buffer the first and second JFETs from capacitances at the gates of the third and fourth JFETs, the fifth JFET having its gate connected to the sources of the first and second JFETs, its source connected to the gates of the third and fourth JFETs, and its drain connected to a negative bias, said sixth JFET having its gate and source connected together and its drain connected to the source of the fifth JFET.

A method of controlling the input bias currents to a first pair of JFETs which are connected in a differential amplifier stage with their sources connected together and their gates adapted to receive respective input voltage signals, comprising:

• cascoding the first pair of JFETs with a second pair of JFETs,
• maintaining the source voltages of the first pair of JFETs substantially equal to the gate voltages of the second pair of JFETs,
• directing a predetermined current no greater than 0.25I.sub.DSS through each JFET, whereby the gate-source voltage of each JFET is maintained at a level at least as great as 0.5V.sub.p, and the gate-drain voltages of the first pair of JFETs are maintained at a level at least as great as V.sub.p, thereby maintaining the first pair of JFETs saturated with a predetermined gate-drain voltage, and
• buffering the first pair of JFETs from capacitances at the gates of the second pair of JFETs.