Process for producing CMOS structures with Schottky bipolar transistors

In a process for forming isolated bipolar transistors, in combination with CMOS transistors, the steps comprising:

• starting with a semiconductor wafer of a first conductivity type;
• depositing a first impurity of an opposite conductivity type and heavy concentration in those regions where bipolar transistors are to be fabricated;
• depositing a second impurity of said first conductivity type and heavy concentration in those regions where CMOS transistors having a channel conductivity of said opposite conductivity type are to be fabricated;
• depositing a layer of epitaxial semiconductor material of said opposite conductivity type over said wafer and said first and second impurity regions;
• depositing a third impurity of said first conductivity type on the surface of said epitaxial layer in those regions where said CMOS transistors having a channel conductivity of said opposite conductivity type are to be fabricated;
• depositing an oxidation resistant coating over said epitaxial layer;
• removing said oxidation resistant coating in the regions between said transistors wherein isolation is desired;
• heating said wafer in an oxidizing atmosphere wherein said semiconductor is oxidized and continuing said heating until said epitaxial layer is approximately penetrated by the resulting oxide, said heating simultaneously acting to cause said second and third impurities to diffuse towards each other to contact each other and thereby from a well of said first conductivity type in said epitaxial layer;
• forming a gate oxide;
• depositing a polycrystalline semiconductor layer over said gate oxide and doping said layer to make it conductive;
• removing said polycrystalline semiconductor layer except in those regions where CMOS transistor gates are desired;
• masking said wafer with a resist having openings located in those regions where CMOS transistors having a channel conductivity of said opposite conductivity type are desired and depositing a fourth impurity of said opposite conductivity type at a heavy dose whereby the polycrystalline gates exposed in said openings are doped and act to self align the deposit to create transistor source and drain regions;
• masking said wafer with a resist having openings located in those regions where bipolar transistor bases and CMOS transistors sources and drains having a channel conductivity of said first conductivity type are desired and ion implanting a fifth impurity of said first conductivity type at a low dose;
• masking said wafer with a resist having openings located in those regions where bipolar transistor base contacts and CMOS transistors sources and drains having a channel conductivity of said first conductivity type are desired and ion implanting a sixth impurity of said first conductivity type to a level of doping substantially higher than that of said fifth impurity;
• depositing a passivating oxide over said wafer thereby to cover said polycrystalline gates, said fourth and fifth impurity deposits, and said bipolar transistor regions;
• masking said wafer with a resist having openings located in those regions where bipolar transistor collector contacts and CMOS transistor back gate contacts are desired, removing said passivating oxide exposed in said mask openings and diffusing a seventh impurity of said opposite conductivity type through the openings thus created in said passivating oxide to an extent where said seventh impurity contacts said first impurity;
• masking said wafer with a resist having openings located where active device contact electrodes are desired for said CMOS and said bipolar transistors and etching holes in said passivating oxide;
• masking said wafer with a resist having openings located in those regions where bipolar transistor emitters are desired and implanting into the thus exposed semiconductor an eighth impurity of said first conductivity type and a ninth impurity of said opposite conductivity type, said eighth impurity being deposited to a level selected to develop the desired bipolar transistor base region and said ninth impurity being deposited to a level in said semiconductor to develop the desired bipolar transistor emitter;
• heating said wafer to activate and diffuse said eighth and ninth impurities;
• and
• applying metallization to said electrodes.