Impedance restoration for fast carry propagation

A multiple bit adder comprised of a plurality of serially connected single bit adders each having two selectable signal paths therein, one of said paths being through a transmission gate switch transistor and the other through a buffer, for propagating a Carry In through said adders to a Carry Out and for deriving a summation signal at each of said serial connected adders, comprising:

• means for connecting multi-bit logic input words A and B to said multiple bit adder such that one bit of A and one bit of B is coupled to each serially connected adder;
• means for connecting a multi-bit impedance restoration mask logic input to said multi-bit adder such that one bit of said multi-bit impedance restoration mask is coupled to each serially connected adder;
• means for connecting a multi-bit bypassed bit control signal to said multi-bit adder such that one bit of said bypassed control signal is connected to each serially connected adder;
• and
• means associated with each of said serially connected adders for passing said Carry In through said adder irrespective of the value of said A and B inputs from the adder having a bypassed bit;
• and
• means for connecting a single bit impendance restoration mask signal to each adder such that the Carry In propagation path through the serially connected adders is routed through a combination of transmission gates and buffers to minimize the propagation delay through said connected adders.

In an associative processor having a plurality of arithmetic cells, each of which cells includes an adder circuit;

• an improved arithmetic adder for minimizing interconnections between cells, said improved adder comprising:
• sum circuit means having first and second data inputs, a carry input and a summation output;
• carry circuit means responsive to said carry input of said sum circuit means for providing a carry signal path having means for providing any one of a plurality of selectable propagation delay times, said propagation delay times being selected in accordance with configuration dependent information and fault location information;
• and
• carry decision logic circuit means coupled to said carry circuit means and responsive to said first and second data inputs adapted to apply carry instructions to said carry circuit.