Jitter reduction circuit for frequency synthesizer

#This invention relates to a frequency synthesizer comprising a reference frequency generator, a frequency control circuit which includes a variable frequency reduction means comprising a cycle cancellation circuit which is arranged to cancel a cycle of the frequency to be reduced by the reduction means for each input pulse to said cancellation circuit from a pulse source, and a jitter compensation signal circuit connected to the frequency control circuit, the output signal of the jitter compensation signal circuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency that would otherwise be caused by each cancelled cycle.

#Such frequency synthesizers are known and are either of the "direct" type in which the output frequency is derived directly from the reference frequency or of the indirect, or phase lock loop type in which the output frequency is generated by a variable frequency oscillator forming part of a phase lock loop which locks the oscillator to a predetermined rational fraction, which is to be understood as including a multiple, of the reference frequency.

#Examples of direct frequency synthesizers are described in U.K. Patent Specifications Nos. 1,545,953 and 2,062,315, and examples of phase lock loop synthesizers are described in U.K. Patent Specifications Nos. 1,447,418 and 2,068,185A. In each type, it is known to include in the frequency reduction means a variable modulus divider to provide the major part of the required frequency reduction. Such dividers generally produce spectrally pure frequencies which are exact subharmonics of the frequency which is to be divided. The frequencies other than subharmonics are produced by a cycle cancellation technique in which selected cycles of the frequency to be reduced are cancelled. Such a technique is well known and is alternatively referred to as sidestep programming (see, for example, A. F. Evers and D. J. Martin, "Improved forms of digital frequency synthesisers", IEE Colloquium Digest 1972/11, pp. 9/1 to 9/5), pulse blanking, pulse removal, pulse cancellation, and pulse or cycle swallowing. The technique is also described in Mullard Technical Note 142 "Versatile LSI frequency synthesiser" pp. 8, 9.

#Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, of which:

#FIG. 1 is a block schematic circuit diagram of a first phase lock loop type of frequency synthesizer,

#FIG. 2 is a block schematic circuit diagram of a similar phase lock loop type of frequency synthesizer including an automatic servo,

#FIG. 1 shows an embodiment of the invention as applied to a frequency synthesizer of the type shown in FIG. 2 of United Kingdom Patent Specification No. 1,447,418, the present references used being the same as in said Figure. The circuit items common to both Figures are a voltage-controlled variable frequency oscillator VFO, a cycle cancellation circuit (pulse swallow) PS, a programmable divider PD, a phase comparator PC, a reference frequency (clock pulse) generator CPG, a successive addition rate multiplier R, a digital-to-analogue converter DA, an amplitude multiplier AM, an analogue summing device ASD, and a low pass filter LPF. The operation of this part of the circuit is fully described in said Patent Specification No. 1,447,418; so only a brief description of the operation of this basic part of the circuit will now be given.

#Items CPG, PC, PD, VFO and LPF form a conventional phase lock loop type of synthesizer in which the frequency Fc of the generator CPG is compared in phase comparator PC with the output frequency Fo after division by divider PD. Any phase difference between the two inputs to comparator PC is represented by a proportionate signal at the output of comparator PC. This signal is integrated in filter LPF to produce a voltage at the control input of oscillator VFO, which voltage causes the phase of the output frequency to change until the two inputs to comparator PC are precisely in phase and Fo=n.sub.1 Fc where n.sub.1 is the modulus of the divider PD.

#In order to provide fractional step sizes, rate multiplier R multiplies the output frequency of divider PD by a factor n.sub.2 .ltoreq.1 and constitutes a pulse source the output pulses of which have an average frequency (pulse repetition rate) F.sub.R each pulse of which causes pulse swallow circuit PS to cancel a cycle of the frequency Fo. Thus, Fo=(n.sub.1 +n.sub.2)Fc.