Stereo amplifier circuit for bichannel signals

A stereo amplifier circuit comprising:

• first circuit means, responsive to first and second input signals, for generating a first output signal which corresponds to the potential difference between said first and second input signals;
• second circuit means, responsive to said first and second input signals, for generating a second output signal which corresponds to the potential difference between said second and first input signals;
• third circuit means, responsive to said first and second input signals, for generating a third output signal which corresponds to the sum of said first and second input signals, said third output signal containing signal components being antiphase to said first and second input signals;
• output circuit means coupled to said first to third circuit means, for providing a first differential output signal corresponding to the potential difference between said first and third output signals, and providing a second differential output signal corresponding to the potential difference between said second and third output signals;
• wherein said first circuit means includes:
• a first transistor having a base receiving said first input signal, a collector coupled to a power source potential and an emitter coupled to a first current source;
• a second transistor having a base receiving a zero-AC potential, a collector coupled via a first collector resistor to said power source potential and an emitter coupled to said first current source;
• and
• a third transistor having a base receiving said second input signal, a collector coupled to the collector of said second transistor and an emitter coupled to a second current source;
• wherein said second circuit means includes:
• a fourth transistor having a base receiving said second input signal, a collector coupled to said power source potential and an emitter coupled to said second current source;
• a fifth transistor having a base receiving said zero-AC potential, a collector coupled via a second collector resistor to said power source potential and an emitter coupled to said second current source;
• and
• a sixth transistor having a base receiving said first input signal, a collector coupled to the collector of said fifth transistor and an emitter coupled to said first current source;
• and wherein said third circuit means includes:
• a seventh transistor having a base receiving said first input signal, a collector coupled via a third collector resistor to said power source potential and an emitter coupled to said first current source;
• and
• an eighth transistor having a base receiving said second input signal, a collector coupled to the collector of said seventh transistor and an emitter coupled to said second source,
• and wherein said first output signal is obtained from the collectors of said second and third transistors, said second output signal is obtained from the collectors of said fifth and sixth transistors, and said third output signal is obtained from the collectors of said seventh and eighth transistors.

A stereo amplifier circuit comprising:

• a first inverting amplifier for invertedly amplifying first input signal and outputting a first inverted signal;
• a second inverting amplifier for invertedly amplifying second input signal and outputting a second inverted signal;
• a first attenuator for attenuating said first input signal with a first attenuation degree and providing a first attenuated signal;
• a second attenuator for attenuating said second inverted signal with a second attenuation degree and providing a second attenuated signal;
• a third inverting amplifier having an inverting input for receiving said first and second attenuated signals, for providing first output signal;
• a third attenuator for attenuating said second input signal with a third attenuation degree and providing a third attenuated signal;
• a fourth attenuator for attenuating said first inverted signal with a fourth attenuation degree and providing a fourth attenuated signal;
• a second amplifier having an inverting input for receiving said third and fourth attenuated signals, for providing a second output signal;
• a fifth attenuator for attenuating said first inverted signal with a fifth attenuation degree, and providing a fifth attenuated signal;
• a sixth attenuator for attenuating said second inverted signal with a sixth attenuation degree, and providing a sixth attenuated signal;
• a third amplifier having an inverted input for receiving said fifth and sixth attenuated signals, for providing a third output signal;
• and
• output circuit means for providing a first differential output signal corresponding to the potential difference between said first and third output signals, and providing a second differential output signal corresponding to the potential difference said second and third output signals.