US 4,536,665 AGranted

Circuit for converting two balanced ECL level signals into an inverted TTL level signal

AssigneeThe Grass Valley Group, Inc.

InventorBirney D. Dayton

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Abstract

A circuit for converting ECL logical signals into TTL logical signals comprises a differential amplifier defining two current paths leading to a negative reference potential source. When the ECL input signal is logical zero, the first current path is closed and the second current path is open, and vice versa when the input signal is logical one. A first transistor has its base connected to the first current path and its emitter connected to a positive reference potential source, and is biased by a load resistor connected to the first current path. A second transistor has its emitter connected to the collector of the first transistor and its base connected to the second current path, and is biased by a second resistor. When the input ECL signal is logical one, the first current path is open and the first and second transistors are on and off respectively, the potential at the output terminal of the circuit being limited by a clamping diode connected between the base and collector of the first transistor. When the input ECL signal is logical zero, the first transistor is non-conductive and the second transistor behaves as an emitter follower, and the potential at the output terminal is close to ground.

Claims12

Dependent claims

A circuit for receiving, at first and second input terminals respectively, a first input logical signal having one of two possible negative potential levels, relative to a ground reference potential level, and a second input logical signal having the other of the two possible negative potential levels, and converting said input logical signals into a logical output signal, having one of two possible positive potential levels, at an output terminal, said circuit comprising:

a switch device defining two current paths which are connectable to a reference potential level that is more negative than either of said two possible negative potential levels, said switch device having a first condition, in which one current path is open and the other is closed, and a second condition, in which said one current path is closed and said other path is open, and being in said first condition when the first input terminal is at the more negative of said two possible negative potential levels and in said second condition when the second input terminal is at the more negative of said two possible negative potential levels;
a first transistor having its base connected to said one current path, the emitter of said first transistor being connectable to a reference potential level that is more positive than either of said two possible positive potential levels;
a first resistor connected between the base and the emitter of said first transistor;
a first diode connected between the base and the collector of said first transistor;
a second transistor having its base connected to said other current path and its emitter connected to said output terminal and to the collector of said first transistor, the collector of said second transistor being connectable to a reference potential level intermediate the less negative of the two possible negative potential levels and the less positive of the two possible positive potential levels;
a second resistor connected between the base of said second transistor and the collector of said first transistor;
and
a second diode having one terminal connected to the base of said second transistor and having its other terminal connectable to a reference potential level intermediate the less negative of the two possible negative potentials levels and the less positive of the two possible positive potential levels.

5 more elements

A circuit for receiving, at first and second input terminals respectively, a first input logical input signal having one of two possible potential levels of one polarity and a second input logical signal having the other of the two possible potential levels of said one polarity, and converting said input logical signals into a logical output signal, having one of two possible potential levels of the opposite polarity, at an output terminal, said circuit comprising:

a switch device defining two current paths which are connectable to a reference potential level of said one polarity and having a greater absolute value than either of said two possible potential levels of said one polarity, said switch device having a first condition, in which one current path is open and the other is closed, and a second condition, in which one current path is closed and said other path is open, and being in said first condition when the first input terminal is at that possible potential level of said one polarity which has the greater absolute value and in said second condition when the second input terminal is at that possible potential level of said one polarity which has the greater absolute value;
a first transistor having its base connected to said one current path and its collector connected to said output terminal, the emitter of said first transistor being connectable to a reference potential level of said opposite polarity and having an absolute value greater than the absolute value of either of said two possible potential levels of said opposite polarity;
a first resistor connected between the base and the emitter of said first transistor;
a first diode connected between the base and the collector of said first transistor;
a second transistor having its base connected to said other current path and its emitter connected to said output terminal and to the collector of the first transistor, the collector of the second transistor being connectable to a reference potential level intermediate that one of the two possible potential levels of said one polarity which has the lesser absolute value and that one of said two possible potential levels of the opposite polarity which has the lesser absolute value;
a second resistor connected between the base of said second transistor and the collector of said first transistor;
and
a second diode having one terminal connected to the base of said second transistor having its other terminal connectable to a reference potential level intermediate said one potential level of said one polarity and said one potential level of said opposite polarity.

5 more elements

Dependencies are inferred from the claim text.