A high speed, non-inverting circuit for providing an interface between TTL logic gates and Schottky transistor logic gates

#The present invention relates generally to bipolar logic circuits and more particularly to a circuit for translating one logic voltage level to another.

#Schottky transistor logic (STL) gates are advantageously used in integrated circuit devices requiring high packing density, high speed, and low power dissipation. In circuits where STL gates must be coupled to transistor-transistor logic (TTL) gates an interface or buffer circuit must be provided since the TTL and STL voltage levels are incompatible. That is, the TTL transistion level is typically between 0.8-2.0 volts while the STL transistion level is about 0.5 volts. Prior interface circuits use TTL gates to perform the required voltage level translation. However, these circuits provide an inverted output and what in some applications is an unacceptably long propagation delay. If a noninverted output is required, an additional inverter must be included in the interface circuit which further increases the propagation delay. In addition, the power dissipation of the TTL interface circuits limits the IC packing density.

#Accordingly, the present invention overcomes many of the disadvantages of prior logic level translation circuits by providing a noninverting interface circuit having minimum power dissipation and propagation delay.

#Other objects and many of the attendant advantages of the present invention will become apparent, and the invention will be better understood, by reference to the following detailed description and appended claims when read in conjunction with the accompanying drawing, which is a schematic diagram of an interface circuit according to one embodiment of the present invention.

#Referring now to the drawing figure, there is shown an interface circuit for translating TTL level input signals to STL levels. In the illustrated embodiment the input is coupled to the cathodes of two high barrier Schottky diodes D1 and D2. The anode of D1 is coupled to the base of an NPN Schottky transistor Q1 which is in turn coupled to an NPN transistor Q2 in an emitter-follower configuration, that is, the collector of Q1 is connected to the collector of Q2 and the emitter of Q1 is connected to the base of Q2. Resistor R2 is connected between the emitter of Q1 and ground and functions as a turn-off resistor for Q2. The emitter of Q2 is coupled to the collector of an NPN Schottky transistor Q4 whose emitter is connected to ground. Transistor Q4 and transistor Q3 form a constant current source, that is, a current mirror, with their bases and their emitters in parallel and the collector of Q3 connected to it base. The collector of Q4 is connected to the cathodes of one or more low barrier Schottky diodes, D6-D.sub.N, the anodes of which form the ouputs of the interface circuit. The voltage swing at the collector of Q4 is limited by clamping the voltage at the base of Q1 by means of diodes D3, D4, D5, and Schottky transistor Q5.

#The output of the interface circuit is connected to the input of an STL gate, for example, Schottky transistor Q6.

#The emitter follower transistors Q1-Q2 and the current mirror transistors Q3-Q4 are connected to the same voltage source, V.sub.2, which supplies the STL gate Q6 that is connected to the output of the interface circuit. The clamp transistor Q5 and the base of Q1 are connected to the voltage source V.sub.1 that supplies the input TTL gates (not shown). Although the interface circuit transistors Q1-Q5 could be connected to a single voltage source V.sub.1, the circuit as shown reduces the power dissipation of transistors Q1-Q4 proportional to the ratio of voltages V2 and V1.