Trench etch process for dielectric isolation

In a process of forming integrated circuit devices in a semiconductor substrate, according to which isolation trenches are produced by selectively etching through at least one trench-defining masking layer and at least one passivating layer disposed above the substrate, in order to reach down to the upper surface of said substrate, subsequent to an initial step of forming a pattern of openings through a conventional uppermost photoresist layer disposed above said trench-defining mask layer, the improvement comprising the steps of:

• first, plasma-depositing SiO.sub.2 to define the trench-defining masking layer;
• interposing between said trench-defining masking layer and said uppermost photoresist layer, a first organic underlayer and a second, barrier layer above said organic underlayer;
• then, creating the conventional pattern of openings through the uppermost photoresist layer, followed by selectively etching corresponding openings in said barrier layer;
• followed by the further step of selectively etching the organic underlayer, by using a highly selective etchant, whereby substantially perfectly vertical walls are produced in the corresponding pattern of openings in the organic underlayer;
• extending said openings by anisotropically etching through said trench-defining masking layer and said passivating layer down to said substrate whereby substantially perfectly vertical walls are produced in the corresponding pattern of openings in the masking layer and passivating layer;
• removing said organic underlayer;
• forming the isolation trenches within the semiconductor substrate by using an anisotropic highly selective etchant to etch into said substrate whereby substantially perfectly vertical walls are produced in the trenches,
• said highly selective etchant being a gas comprising SF.sub.6,CL.sub.2 and an inert gas,
• removing said trench-defining masking layer by the use of an HF solution such that the high etch ratio, which obtains between the plasma-deposited trench-defining masking layer of SiO.sub.2 and the passiating layer of SiO.sub.2 when such HF solution is used, precludes significant etching of said passivating layer, and
• opening device contact holes in said passivating layer without the use of masking to protect said walls of said trenches.