Series current limiter
AssigneeMotorola, Inc.
InventorLeland T. Brown
Life of this patent
Estimating the term…
Abstract
Field effect transistors are used in a series current limiter circuit. The field effect transistors are depletion type transistors and are interconnected in a manner to decrease conduction when an overvoltage or overcurrent condition is sensed. Biasing resistors are used to maintain the transistors in a non-conductive state until the overvoltage or overcurrent condition is removed.
Claims7
A series current limiter circuit having a first terminal and a second terminal, comprising:
- a first field effect transistor having a first current carrying electrode coupled to the first terminal and a second current carrying electrode coupled to a node, and a control electrode coupled to the second terminal;
- a second field effect transistor having a first current carrying electrode coupled to the node and a second current carrying electrode coupled to the second terminal;
- a first resistor coupled between the node and the control electrode of the first field effect transistor;
- a second resistor coupled between the node and a control electrode of the second field effect transistor;
- a third resistor coupled between the first terminal and the control electrode of the second field effect transistor;
- and means for clamping a voltage coupled between the second terminal and the control electrode of the second field effect transistor.
A series current limiter circuit for protecting against an overcurrent and having first and second terminals, comprising:
- first and second means for controllably limiting current flow therethrough, the first and second means being coupled in series between the first and the second terminal;
- a current source for sourcing a limited amount of current coupled in parallel with the first means;
- a first resistance coupled in series with the current source;
- and a second resistance coupled in parallel with the second means.
A circuit for limiting current flow in both directions between a first and a second terminal, comprising:
- first, second, third and fourth field effect transistors all coupled in series between the first and second terminals, and forming a first node between the first and second field effect transistors and a second node between the third and fourth field effect transistors;
- a first resistance coupled between the second and third field effect transistors and having a first end coupled to the second field effect transistor and a second end coupled to the third field effect transistor;
- a first current source for supplying a low current coupled in parallel to the first transistor;
- and a second current source for supplying a low current coupled in parallel with the fourth transistor.
Dependencies are inferred from the claim text.