Synchronization of real-time clocks in a packet switching system

contents. 15. The arrangement of claim 14 wherein said remote processor means further responsive to a second set of program instructions for replacing another group of bit signals of said contents of said one of said real-time clocks with a corresponding group of said other one of said real-time clock means' transmitted bit signals to synchronize said other group of bit signals of said contents with the corresponding group of bit signals of said other one of said real-time clock means;

• and
• said remote processor means further responsive to a third set of program instructions for adding a predefined set of bit signals to said other group of bit signals of said contents upon the group of said other one of said real-time clock means' transmitted bit signals being numerically greater than the updated group of bit signals of said contents to synchronize the other group of bit signals of said contents with the present corresponding group of bit signals of said other one of said
• real-time clock means. 16. An arrangement for synchronizing a plurality of real-time clock means via a packet switching system with each of said real-time clock means being controlled by an individual one of a plurality of processor means, comprising
• one of said processor means controlling one of said real-time clock means responsive to a first set of program instructions for assembling an interrupt packet comprising the least significant bit signals of said one of said real-time clock means for transmission to another one of said processor means;
• said other one of said processor means controlling another one of said real-time clock means responsive to said interrupt packet and a second set of program instructions for calculating bit signals representing the difference between the transmitted least significant bit signals and the least significant bit signals of said other one of said real-time clock means;
• said other one of said processor means responsive to a third set of program instructions for assembling a data packet comprising bit signals representing the state of said other one of said real-time clock means and the difference bit signals for transmission to said one of said processor means;
• said one of said processor means responsive to the receipt of said data packet and a fourth set of program instructions for adding said difference bit signals to bit signals representing the state of said one of said real-time clock means to form sum bit signals;
• said one of said processor means responsive to the formation of said sum bit signals and a fifth set of programmed instructions for adding a predefined set of bit signals to the most significant bit signals of said sum bit signals upon the transmitted least significant bit signals of said other one of said real-time clock means being numerically greater than the least significant bit signals of said sum bit signals;
• and
• said one of said processor means responsive to a sixth set of program instructions for storing said sum bit signals into said one of said real-time clock means to update the latter to the present state of said
• other one of said real-time clock means. 17. The arrangement of claim 16 wherein said fourth set of program instructions comprises a subset of program instructions and said one of said processor means further responsive to said subset of program instructions for replacing the most significant bit signals of said sum bit signals with the transmitted most significant bit signals of said other one of said real-time clock means.