Data processing system

A data processing system comprising:

• (a) a plurality of processors;
• (b) a communication bus for connecting all of said processors together;
• (c) a bus arrangement comprising a plurality of additional buses;
• (d) means for connecting any processor of a sub-set of said plurality of processors in controlling relation to said bus arrangement whereby any processor of said sub-set can control said bus arrangement, said sub-set dividing the plurality of processors into two groups of processors;
• (e) each group of said processors being capable of using the other group of processors as a pool so that whatever function is performed by said other groups of processors can be assigned to a processor of said other group whose identity is not known to the assigning group of processors;
• and
• (f) each individual processor of said plurality of processors being capable of communicating with each other individual processor through said communication bus, the message of said communication bus containing source identification bits and destination identification bits and each processor recognizing one or more of said identification bits, one of said bits being that processor's own identification bit and the other of said bits being a pool identification.

A data processing system comprising:

• (a) a plurality of tightly coupled processors;
• (b) main storage means separate from said processors;
• (c) main store bus means operatively connected to main storage means and to said processors for enabling said processors to share said main storage means;
• (d) communication bus means separate from said main store bus means for connecting all of said processors together in a tightly coupled manner with all of said processors sharing a common memory space and in a manner such that any processor can identify any other processor and thereby communicate with any other processor at high speed commensurate with the single instruction speed of any one processor in order to transfer control information and data associated with the control information through said system;
• (e) a supervisory processor;
• and
• (f) diagnostic bus means separate from said main store bus means and said communication bus means connected to and controlled by said supervisory processor for connecting said supervisory processor to all of said processors in said system for initiating, configuring and monitoring said system through said diagnostic bus means.

A data processing system comprising:

• (a) main storage means;
• (b) main storage bus means connected to said main storage means;
• (c) a supervisory processor connected to said main storage bus means;
• (d) at least one other processor, said other processor being connected to said main storage bus means, said other processor having its own storage means so that it does not use said main storage means as a programmed storage;
• (e) communication bus means separate from said main store bus means connected to said supervisory processor and to said other processor;
• (f) diagnostic bus means separate from said main store bus means and from said communication bus means connected in controlled relation to said supervisory processor for connecting said supervisory processor to said other processor in said system for initiating, configuring and monitoring said system through said diagnostic bus means;
• and
• (g) an input-output bus ensemble connected to said supervisory processor and to said other processor, said other processor capable of being limited to providing transfer of information between said input-output bus ensemble and said main storage means;
• (h) whereby said system has the capability of including additional ones of said other processors, said additional processors being of the same or of different types.

A data processing system comprising:

• (a) an intelligent main store including main memory means, main memory control means connected to said main memory means for accessing said memory means and function means connected to said control means for providing memory management functions;
• (b) main storage bus means connected to said main store;
• (c) at least one execution processor connected to said main storage bus means for fetching, decoding and executing instructions;
• (d) at least one auxiliary processor connected to said main storage bus means for providing services not performed by said execution processor including systems support, input-output processing and special instruction support;
• (e) a supervisory processor connected to said main storage bus means;
• (f) communication bus means connected to said auxiliary and execution processors and to said supervisory processor;
• (g) diagnostic bus means connected in controlled relation to said supervisory processor for connecting said supervisory processor to each of said auxiliary and execution processors for initiating, configuring and monitoring said system through said diagnostic bus means;
• (h) an input-output bus ensemble comprising an arrangement of a plurality of input-output buses connected to said supervisory processor and to said auxiliary processor, said auxiliary processor capable of being limited to providing transfer of information between said input-output bus ensemble and said main store means, and said execution processor capable of being limited to providing computational functions not involving information transfer from said input-output bus ensemble;
• and
• (i) at least one direct memory access controller connected to said main storage bus means and to said input-output bus ensemble.