Method of characterizing reliability in bipolar semiconductor devices

Abstract

This invention concerns a method of characterizing the reliability in bipolar semiconductor devices having reliability detracting leakage current due to a parasitic FET transistor between the p-type isolation (source) and base regions (drain) of the bipolar, NPN transistor. The source of this PNP parasitic FET transistor, i.e., the isolation region and the gate are provided with electrodes and the drain region and gate electrodes short-circuited. Then, a reliability function R is determined as equal to the product N.sub.SS .times.N.sub.eff .times.N.sub.D 1/2, wherein N.sub.SS, is the interface charge density, N.sub.eff, is the oxide charge density, and N.sub.D, is the impurity concentration in the epitaxial layer. This function is correlated with the time-to-fail, such as, for instance, T.sub.50. It suffices to characterize the manufacturing line beforehand by plotting curve R=f(T.sub.50); to this end, the reliability functions and their respective times-to-fail after a burn-in step, are measured for different batches of wafers. Then, it suffices to measure the reliability function for any given batch and to deduce therefrom, according to the curve, the time-to-fail, directly. Such a method makes it possible to save time on the pilot lines while a novel bipolar semiconductor product is being developed, and to have a very rapid reaction time on the manufacturing lines, when such a reliability defect occurs.

Dependencies are inferred from the claim text.