US 4,517,512 AGranted

Integrated circuit test apparatus test head

AssigneeMicro Component Technology, Inc.

InventorsDennis M. Petrich, Christopher G. Amick, Stanley L. Gruenenwald

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Abstract

An improved test system for performing DC and AC parametric and dynamic functional testing of multi-terminal integrated circuits is described. All of the circuitry for producing and responding to D.C. and high-integrity stimulus and response test signals is located within a Test Head module sized for use in close proximity of the device under test. A high-integrity bus in the Test Head interconnects the high-integrity producing and handling circuits, with inexpensive connectors and batch-fabricated printed circuit board techniques. A Controller provides digital test commands for energizing the test signal producing cirucits within the Test Head and for evaluating the test results. The control and measurement signals passing between the Controller and the Test Module require no special conductor implementation techniques. A unique detachable, modularized bussing scheme between the Controller and Test Head and within the Test Head enables the test system to be manufactured at minimum cost, while maximizing reliability, signal integrity and manufacturing repeatability from system to system and enables rapid replacement and interchangability of test circuits and functional capabilities without sacrificing the quality of bus structure that carries the high integrity signals.

An automated test apparatus for testing various parameters of multiple-terminal integrated circuit devices at a test station by communicating with the terminals of a device via high-integrity test signals, each involving communication with a single terminal of the device, and via shared function signals, involving communication with all terminals of the device, comprising:

(a) A test head module, comprising:
(i) a chassis, sized and configured for ease of placement and use at a test station, having a test port configured for placement in direct proximity to the terminals of an integrated circuit device to be tested;
(ii) a plurality of discrete circuits mounted in said chassis proximate said test port, each of said circuits being responsive to received control signals and including means for generating and transmitting, and receiving high-integrity test signals communicated to and from, respectively, a corresponding terminal of the device at the test station to which said circuit is dedicated, each of said circuits being uniquely identifiable with, and having a signal output for, a different one of the terminals of the device;
(iii) at least one common circuit electronically communicating with each of said discrete circuits, said at least one common circuit being responsive to received control signals and including means for generating and transmitting, and receiving shared function signals communicated to and from, respectively, all terminals of the device via said discrete circuits;
(iv) means for operatively connecting said plurality of discrete circuits at said test port with said corresponding terminals of said integrated circuit device;
(b) controller means for producing said control signals to selectively activate said discrete circuits and said at least one common circuit, said controller means being operable to produce said control signals in a manner enabling simultaneous activation of a plurality of said discrete circuits and said at least one common circuit;
and
(c) means operatively connecting said controller means with said plurality of discrete circuits and said at least one common circuit for carrying said control signals therebetween.

5 more elements

Facts

Application

06/381,736Filed 24 May 1982

Granted

14 May 1985

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G01R 31/3004
Marginal testing, e.g. by varying supply voltage: current or voltage test
G01R 31/2851
Testing of electronic circuits, e.g. by signal tracer: testing of integrated circuits [IC]
G01R 31/31905
Tester configuration: interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
G01R 31/2886
Testing of integrated circuits [IC]: features relating to contacting the IC under test, e.g. probe heads; chucks

Abstract

Claims43