Fast lock PLL having out of lock detector control of loop filter and divider

A frequency synthesizer having a phase locked loop adapted for fast recovery of phase lock comprising:

• a reference source;
• a phase detector connected to an output of the reference source to produce an output that is a measure of a phase difference;
• a low-pass filter connected to the phase detector to filter the output of the phase detector;
• a voltage-controlled oscillator connected to the low-pass filter, the filtered output of the phase detector connected as a control voltage to control the voltage-controlled oscillator;
• a frequency divider means for producing a divided output signal proportional to an output of said voltage-controlled oscillator, said divided output signal coupled to the phase detector for comparison with the output of the reference source to produce the measure of the phase difference;
• and
• means for controlling a divisor of said frequency divider means so that said divisor is a first number when said phase difference is less than a predetermined range, is a second number not equal to said first number when said phase difference is within said range, and is a third number not equal to said first or second numbers when said phase difference is greater than said range, said first and third numbers selected to cause said phase difference to rapidly come within said range, said phase locked loop not being in phase lock when said phase difference is less than and greater than said range.

A frequency synthesizer having an output signal, adapted for increased speed of recovery of phase lock in a phase locked loop of the synthesizer comprising:

• means for sensing the difference in phase between a reference signal and other signal derived from said output signal;
• means for detecting if said difference is within a predetermined range, is less than said range, or is greater than said range, said phase locked loop not being in lock when said difference is either less than or greater than said range;
• means for changing a divisor of a frequency divider in the phase locked loop to a first number if said difference is less than said range;
• and
• means for changing said divisor to a second number different than said first number if said difference is greater than said range, said first and second numbers selected to cause said difference to rapidly come within said range thereby increasing the speed of recovery of phase lock.