VLSI Chip with ground shielding
AssigneeAT&T Bell Laboratories
InventorMasakazu Shoji
Life of this patent
Estimating the term…
Abstract
In VLSI chips, clock pulse skew is increasingly forbidding as one micron technology and operation at 25 megahertz is approached. Skew is avoided by encompassing the clock distribution line in such chips with ground lines to shield the distribution line from capacitive coupling to adjacent control lines. Skew is reduced dramatically.
Claims4
An integrated circuit chip having a wiring section including at least one clock distribution line and at least a first signal line, said wiring section including first and second lines adjacent to first and second sides of said clock distribution line, each of said first and second lines being adapted to be maintained at a fixed d-c potential for isolating said clock distribution line from said first signal line.
Dependencies are inferred from the claim text.