Digital processor with floating point multiplier and adder suitable for digital signal processing

A digital processor comprising:

• a first data bus having a first number of bit lines;
• interface means connected to said first data bus for receiving data to be provided on the first data bus and for transmitting data provided on the first data bus;
• data storage means connected to said first data bus for storing data provided on the first data bus, each data having said first number of bits;
• read means connected to said data storage means for simultaneously reading first and second data from said data storage means;
• multiplication means for performing floating point multiplication on first and second data read out by said read means and both having floating point representation, and for delivering produce data with floating point representation and with a second number of bits which is larger than the first number of bits;
• a second data bus having said second number of bit lines;
• floating point addition means including input selection means connected to said multiplication means and said second data bus for selecting a pair of operands from the first and second read out data, the product data and data on the second data bus, extending means for selectively extending the first and second read out data into floating point data of a second number of bits when said input selection means selects either of the first and second read out data and operation means for performing floating point addition on said selected pair of operands:
• transferring means connected to said operation means of said floating point addition means for selectively transferring the sum data provided therefrom onto said first or second data bus;
• converting means connected to said transferring means for converting the sum data into floating point data having said first number of bits when it is necessary to provide the sum data onto the first data bus;
• memory means for storing a plurality of program instructions;
• and
• control means responsive to program instruction read out from said memory means for controlling the operations of said interface means, said data storage means, said read means, said multiplication means, said floating point addition means, and said transferring means.