Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors

A method for the manufacture of integrated MOS field effect transistor circuits, comprising the steps of:

• (a) manufacturing structured SiO.sub.2 layers on a p-doped semiconductor substrate for separation of the active transistor regions according to a so-called LOCOS method or iso-planar method;
• (b) forming a gate insulating layer by oxidation of a free portion of the p-substrate surface;
• (c) depositing an entire-surface polysilicon layer comprised of n.sup.+ doping substances and structuring the polysilicon gate therefrom;
• (d) removing the gate oxide layer in a region of the substrate surface not covered by the gate;
• (e) depositing an SiO.sub.2 layer from the gas phase with a CVD-method;
• (f) anisotropically etching the SiO.sub.2 -layer so that edges of the silicon gate remain covered by the oxide;
• (g) carrying out an arsenic ion implantation at the substrate surface on both sides of the gate for the production of the monocrystalline n.sup.+ -doped source and drain zones in the p-doped substrate;
• (h) depositing in self-adjusting manner tantalum silicide from the gas phase pursuant to use of a reaction gas mixture which produces hydrogen chloride during the reaction, so that the tantalum silicide is deposited only on the surface regions of the substrate which are comprised of silicon and not on insulating layers since crystal nucleus formation is suppressed there;
• (i) depositing an insulation layer acting as an intermediate oxide;
• (j) etching hole contact regions for the exterior contact metal printed conductor to the silicized silicon source or drain zones of the substrate;
• and
• (k) carrying out metallization and structuring of the exterior contact metal printed conductor.

A method for the manufacturing of integrated MOS field effect transistor circuits, comprising the steps of:

• (a) manufacturing structured SiO.sub.2 layers on a p-doped semiconductor substrate for separation of active transistor regions according to a so-called LOCOS method or isoplanar method;
• (b) carrying out a gate oxidation through oxidation of a free portion of the p-substrate surface;
• (c) depositing an entire-surface polysilicon layer and doping this layer with n.sup.+ -doping substances;
• (d) depositing a silicon nitride layer on the polysilicon layer and structuring this double layer comprised of the silicon nitride layer and polysilicon layer to form the gate;
• (e) carrying out a thermal oxidation whereby an oxide layer develops on free surfaces of the silicon substrate, and at edges of the highly-doped polysilicon gate a thicker oxide layer being formed than on the substrate;
• (f) carrying out an arsenic-ion implantation in the transistor region for generation of monocrystalline n.sup.+ -doped source and drain zones in the p-doped substrate;
• (g) removing the nitride layer;
• (h) conducting an entire-surface etching-away of the oxide layer on the substrate surface until the substrate is exposed;
• (i) depositing in self-adjusting manner a tantalum silicide layer from the gas phase by use of a reaction gas mixture which produces hydrogen chloride during the reaction, so that the tantalum silicide is deposited only on the surface regions of the substrate which are comprised of silicon and not on insulating layers since crystal nucleus formation is suppressed thereon;
• (j) depositing on the structure completed thus far an insulating layer acting as an intermediate oxide;
• (k) etching contact holes to permit the exterior metal printed conductor to contact at least one of the silicized silicon zones of the substrate;
• and
• (l) carrying out metallization and structuring of the exterior contact metal printed conductor.

A method for the manufacture of integrated MOS field effect transistors in silicon gate technology, comprising the steps of:

• providing a silicon substrate;
• forming in and at a surface of the silicon substrate insulation regions to define an active transistor region, and providing a thin gate oxide layer at the active transistor region;
• providing a polysilicon gate over the gate insulating layer and providing insulation at side-walls of the gate;
• doping the substrate at both sides of the gate to form drain and source zones;
• producing in self-adjusting fashion by use of the insulation a metal silicide layer to render the diffused drain and source zones low-impedance by selectively depositing from a gas phase only onto surfaces of the silicon drain and source zones and gate and not onto the insulation by using a reaction gas mixture comprising a silane compound along with a hydrogen halide during thermo-decomposition, a crystal nucleus formation on the insulation being suppressed;
• providing an insulating layer over the metal silicide layer;
• and
• forming a contact hole through the insulating layer to a portion of the metal silicide layer for contacting the silicide layer to external metallization.