Programmable logic apparatus for entering, processing and transmitting data
AssigneeFordahl S.A.R.L.
InventorsJean Engdahl, Jerome Formaz
Life of this patent
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Abstract
Logic apparatus for presenting results or commanding actions on the basis of furnished informtion. The apparatus includes three distinctive memories which are interrogated cyclically and in synchronism. The first distinctive memory contains instructions, while the second memory contains masking grid signals. The third memory contains pairs of input and output addresses. A logic comparator determines if a prerequisite condition is satisfied and distinctive channels or buses are used for intercommunication. A first bus applies inputs to the comparator, a register or an output unit; a second bus applies grid signals to the comparator, a register, or an output; and a third bus sends addresses to input and output units.
Claims10
Programmable logic apparatus comprising
- first memory means for storing only instruction signals;
- second memory means, separate from said first memory means, for storying only grid signals which permit said instruction signals to be taken partly or completely into account;
- third memory means, separate from said first memory means and said second memory means, for storing only pairs of address signals at each storage location of said third memory means;
- means for addressing said first memory means, said second memory means and said third memory means cyclically and in synchronism for simultaneously extracting (1) a set of instruction signals, (2) a set of grid signals for partly or completely modifying said instruction signals and (3) a pair of different address signals;
- and means for comparing said instruction signals and said grid signals for determining if a prescribed condition is satisfied for the continuation of processing.
The method of operating logic apparatus which comprises the steps of:
- (a) storing only instructions signals in a first memory;
- (b) storing only grid signals, which permit said instructions signals to be taken partly or completely into account, in a second, separate memory;
- (c) storing a pair of different address signals at each storage location in a third memory which is separate from said first memory and said second memory;
- (d) addressing said first memory, said second memory and said third memory cyclically and in synchronism for simultaneously extracting (1) a set of instruction signals, (2) a set of grid signals for partly or completely modifying said instruction signals, and (3) a pair of different address signals;
- and
- (e) comparing at least said instruction signals and said grid signals for determining if a prescribed condition is satisfied for continuing the operation of said logic apparatus.
Dependencies are inferred from the claim text.