Programmable sequence controller
AssigneeToyoda Koki Kabushiki Kaisha
InventorsToshihiko Yomogida, Yasuo Suzuki, Kyoji Ito
Life of this patent
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Abstract
A programmable sequence controller using a technique called microprogramming, including a microprogram memory having a plurality of memory sections each storing a set of microinstructions corresponding to the command word of a sequence instruction. The operation code of the sequence instruction is applied to the upper bits of the microprogram memory so as to select one of the memory sections. The remaining bits are determined by a counter and the ON/OFF state of an I/O element so that one of the microinstructions is read out from the selected memory section.
Claims7
A programmable sequence controller comprising:
- instruction generating means for successively and cyclically generating a plurality of sequence instructions each composed of an operation code for designating a type of instruction and an operand for designating one of input and output elements;
- an I/O circuit section connected to said input and output elements and responsive to said operand of each generated sequence instruction for selecting one of said input and output elements;
- a microprogram memory having a plurality of memory sections, address input terminals and signal output terminals, each of said memory sections comprising a plurality of memory addresses for respectively storing microinstructions;
- a counter;
- counter control means connected to said counter for successively incrementing the content of said counter;
- test flag means responsive to signals output from a first part of said signal output terminals for temporarily storing the result of a test on the ON-OFF state of at least one of said input and output elements;
- first line means for applying said operation code from said instruction generating means to a first part of said address input terminals so as to select one of said memory sections;
- second line means for applying the content of said counter to a second part of said address input terminals;
- third line means for applying the status of said test flag means and the ON-OFF state of one of said input and output elements selected by said I/O circuit section, to a third part of said address input terminals, said second and third line means enabling said microprogram memory to select one of said memory addresses composing a selected one of said memory stations;
- fourth line means for applying a signal from a second part of said signal output terminals to said counter so as to reset the same;
- and
- fifth line means for applying a signal from a third part of said signal output terminals to said I/O circuit section so as to energize or deenergize one of said output elements selected by said I/O circuit section.
Dependencies are inferred from the claim text.