High density Josephson junction memory circuit

A high density Josephson junction memory circuit comprising:

• a substrate,
• a ground plane pattern on said substrate,
• said ground plane pattern comprising a plurality of holes arranged in columns and rows,
• dielectric insulator pads deposited in said holes of said ground plane pattern to form a planar surface,
• a plurality of memory cells mounted on said planar surface,
• each said memory cell comprising a storage loop having a biasing gate current source, a low reference voltage source and a storage loop connected between said current source and said voltage source,
• said storage loop having a first branch and a second branch connected in parallel,
• a single Josephson junction device in said first branch,
• said Josephson junction device being located on a dielectric insulator pad,
• an inductive reactance in said first branch and an inductive reactance in said second branch of equal magnitude,
• an X current control line inductively coupled to each said Josephson junction device,
• a Y current control line inductively coupled to each said Josephson junction device,
• said coupling between said X and said Y control lines and each said Josephson junction device being separated from said ground plane pattern so that the threshold characteristic of said Josephson junction device is symmetrical with respect to said biasing gate current, and
• sensing means inductively coupled to said second branch of said storage loop for sensing the magnitude of the current flowing in said loop of said memory cell.