Associative processor with variable length fast multiply capability
AssigneeInternational Telephone and Telegraph Corporation
InventorJohn M. Cotton
Life of this patent
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Abstract
An associative processor is described wherein an array of associative processing cells is configured to achieve variable length multiplication of numbers, such as binary two's complement numbers, under mask control. A configuration suitable for signal multiplication is described wherein the processing sequences in all cells are compatable, each to the other, whether the cells are at the edges or the middle of an array row, and regardless of the computational sequences required to be performed. An associative cell structure is described, including an improved arithmetic logic unit having separate carry and borrow save paths which may be enabled and active simultaneously or alternately.
Claims21
An associative processor comprising:
- an array of rows and columns of associative cells, each of said cells being adapted to simultaneously store a sum bit and a carry bit, and each of said cells including:
- masking means for identifying that one or more particular cells contains either a multiplier or a multiplicand bit or any combination thereof;
- means for storing a multiplicand bit;
- means for multiplying the multiplicand bit with a multiplier bit;
- means for enabling said cell during a multiplication operation such that said cell stores two bits of the multiplication result;
- arithmetic logic unit means for serially receiving multiplier bits for adding or subtracting said masked multiplicand bit to the results of the arithmetic operation from the previous shift time to derive a current multiplication result;
- and
- means for coupling said current multiplication result to the adjacent associative cell in the same shift time in which the current result is obtained, such that multiplication occurs simultaneously in adjacent cells for a multiplicand of arbitrary digit length and a multiplier of fixed or variable length.
A method of fast multiplication of variable length binary numbers in an associative processing array of associative processing cells comprising the steps of:
- storing a plurality of binary instructions, each instruction including an operation field, a data field and a masking field;
- enabling and disabling individual of said processing cells in accordance with said masking field to implement a fast multiplication operation in arithmetic logic units of each cell on serial multipliers coupled to said cells under the control of said operation field;
- multiplying the multiplicands with multiplier bits to obtain a fast multiplication input to the arithmetic logic units of the cells;
- coupling said multiplicands in parallel and said multiplier bits serially to an arithmetic logic unit in each of said associative array cells to derive multiplication product result;
- and
- coupling said multiplication product result in each cell to the adjacent cell in the same shift time such that multiplication is performed simultaneously in each cell for multiplicands and multipliers of arbitrary digit length.
Dependencies are inferred from the claim text.