Battery saver for a paging receiver or the like _

In a portable radio communication apparatus responsive to a digital preamble code and a digital identification code and comprising, a receiver section, a power supply means, and a battery saving circuit, said battery saving circuit including decoder means selectively producing a control signal to control the supply of power from said power supply means to said receiver section, said decoder means comprising:

• means for comparing the digital preamble code on a bit-by-bit basis with a first predetermined digital code;
• means for producing an error signal each time corresponding bits of said digital preamble code and said first predetermined digital code do not coincide;
• means for adding each produced error signal to previously produced error signals as soon as the error signal is produced to provide a continuously updated count of error signals produced during the bit-by-bit comparison of the digital preamble code with the first predetermined digital code;
• and
• means for suspending said control signal as soon as the count of said error signals reaches a preset number;
• means for maintaining said control signal for a predetermined time when each bit of said digital preamble code coincides with each bit of said first predetermined digital code;
• and
• means for comparing said digital identification code with a second predetermined digital code after detecting coincidence between said digital preamble code and said first predetermined digital code.

A method for selectively supplying power to a receiver section of a digital communication apparatus, said receiver section receiving a carrier wave which is modulated with a digital preamble and a digital identification code, said method comprising:

• periodically beginning the supply of power to said receiver section;
• detecting a first coincidence between the received digital preamble and a first predetermined code on a bit-by-bit basis;
• stopping said supply of power if it is determined that the error number of the bit-by-bit basis detection exceeds a predetermined number;
• and
• continuing said supply of power for a first predetermined period of time if said error number is less than said predetermined number.

A battery saving circuit for use in a portable radio communication apparatus, said apparatus including receiver section means for receiving a carrier wave which is modulated with a digital preamble code of logic "1"'s and "0"'s and a digital identification code, waveform shaper means for producing a digital output signal representative of said digital preamble and said digital identification codes, power supply means for supplying power to said receiver section means in response to a first control signal, and a clock means, said battery saving circuit including decoder means responsive to the output of said receiver section means for respectively detecting a first coincidence between the received preamble code and a first predetermined code and a second coincidence between the received identification code and a second predetermined code, and selectively providing said first control signal to said power supply means, wherein said decoder means further includes;

• (a) means for synchronizing the clock of said battery saving circuit with a digital output from said waveform shaper means;
• (b) means for detecting said first coincidence on a bit-by-bit basis, said detecting means including:
• (i) first means for determining, after the establishment of synchronization, whether or not said digital output is a "1" bit;
• (ii) timer means for producing a first timer period;
• (iii) means for starting said timer means after waiting one bit if said first means for determining signifies said digital output is a "0" bit and for immediately starting said timer if said digital output in a "1" bit;
• (iv) second means for determining, after the start of said timer, whether or not said digital output is a "0" bit;
• (v) third means for determining, after the start of said timer and after determining if said digital output is a "0" bit, whether or not said digital output is "1";
• (vi) means for causing said second and third determining means to repeat their operations at least one time;
• and
• (c) means for suspending the provision of said first control signal to said power supply means when said second and third determining means of said detecting means indicate at least a predetermined number of negative responses.