Variable digital delay circuit
AssigneeAllied Corporation
InventorsRonald P. Miller, William H. Chiles, Bill L. Masteller
Life of this patent
Estimating the term…
Abstract
A variable digital delay circuit is disclosed which utilizes a shift register to periodically sample a signal to be delayed and after a predetermined number of samples are collected as a group of zeros and ones making up a binary word the word is stored in parallel in a memory. After each binary word is stored in a memory a binary word previously stored in the memory is read out into a buffer store from which each individual bit is sequentially read out using a multiplexer at the same rate that the bits were originally taken to thereby recreate the original signal samples. The time delay is determined by how long the previously stored binary word being read out has been stored in the memory.
Claims10
A variable digital delay circuit comprising:
- timing means including timing signal generation means;
- means for periodically sampling a signal to be delayed by a predetermined period of time;
- memory means for storing each signal sample taken by said sampling means following taking the sample;
- and
- means for reading a previously stored signal sample out of said memory means immediately following storing a signal sample therein, each signal sample being read out of said memory means having been stored therein a selected period of time determined by the timing signal generation means before being read out, the selected period of time corresponding to said predetermined period of time;
- the timing means controlling said sampling means, said memory means and said reading means.
Dependencies are inferred from the claim text.