Interlaced programmable logic array having shared elements
AssigneeInternational Business Machines Corporation
InventorsHoward L. Kalter, Francis W. Wiedman
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Abstract
A programmable PLA circuit in which an interlaced AND/OR array is provided which has both common input and common output lines. Separate AND and OR functions are generated during two different timing intervals such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval and to provide the Exclusive-NOR of sum of product terms or the sum of the Exclusive-NOR of product terms during the second time interval.
Claims10
In a programmable logic array circuit including a first logic array responsive to first input signals for providing first output signals corresponding to the logical product terms of selected input signals during a first time interval and second logic array responsive to second input signals to provide during a second time interval output signals corresponding to sums of selected product terms provided by the first logic array, each logic array including a plurality of input lines and a plurality of output lines, the improvement characterized in that at least some of the input lines of both of the first and second logic arrays are physically common and at least some of the output lines of both the first and second logic arrays are physically common, said programmable logic array circuit including first logic means for providing logical representations of the logical product terms generated by the first logic array to the common input lines to generate a sum of product terms on the output lines during the second time interval.
A programmable logic array circuit for implementing the binary addition of a pair of n-bit binary numbers including a plurality of input decoders responsive to corresponding bits of said binary numbers for generating simple binary addition logical functions, a logical AND array responsive to said functions for generating a plurality of product terms and a logical OR array responsive to a plurality of input signals for generating a plurality of sum terms, the improvement comprising:
- a plurality of Exclusive-NOR circuit means for generating logical Exclusive-NOR functions in response to pairs of input signals;
- a plurality of NOR circuit means for generating logical NOR functions in response to input signals;
- first means for coupling selected pairs of product terms to the inputs of at least one Exclusive-NOR circuit means;
- second means for coupling the inputs of at least said one of said Exclusive-NOR circuit means to at least one of said NOR circuit means;
- third means for coupling selected paris of sum terms to at least one of said Exclusive-NOR circuit means;
- and
- fourth means for coupling the output of at least one of said Exclusive-NOR means to an output circuit, said output being representative of at least one of the output bits of the sum of the n-bit binary number to be added.
Dependencies are inferred from the claim text.