Oxide trench structure for polysilicon gates and interconnects

Abstract

Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate. In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation. Then, low temperature thermal oxidation is accomplished growing a thick oxide over the polysilicon gate sidewalls and a thin oxide over the source-drain regions. The mask over the gate and the thin oxide over the source-drain regions is removed and by ion implantation heavily doped source-drain regions are formed in the previously formed lightly doped source-drain regions not masked by the polysilicon sidewall oxide. Selective deposition of a metal is then accomplished over the source-drain regions of the silicon substrate and the polysilicon gate.

Dependencies are inferred from the claim text.