Counter circuit for counting high frequency pulses using the combination of a synchronous and an asynchronous counter

Abstract

The counter circuit is adapted to counting high frequency pulses and to being read while counting said pulses. It comprises a plurality of pulse counting stages of increasing numerical significance, and read means for reading the states of said stages. Said plurality of pulse counting stages comprises lower significance stages (10.sub.1 to 10.sub.4) connected as a synchronous counter (10) and higher significance stages (12.sub.1 to 12.sub.n) connected as a ripple counter (12). The synchronous counter is so connected that it counts the high frequency pulses (H) directly, and that any change of state required in any of its stages on counting a pulse occurs substantially simultaneously with the arrival of said pulse. The ripple counter is so connected that it counts count cycles of the synchronous counter, and that it takes a long time relative to the interval separating two successive high frequency pulses for a change of state to propagate, where necessary, from the least significant stage (12.sub.1) of the ripple counter to its most significant stage (12.sub.n). Early count signal means (24.sub.4) are provided to apply a count signal to the ripple counter during each count cycle of the synchronous counter at an instant which is early relative to the synchronous counter cycling from its full count to its empty count. Further, the read means (49) are provided with read timing means (24.sub.4 and 57) for causing the state of the ripple counter to be read regularly at a predetermined synchronous counter state.

Dependencies are inferred from the claim text.