US 4,498,177 AGranted

M Out of N code checker circuit

AssigneeSperry Corporation

InventorBrian R. Larson

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Abstract

An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln.sub.2 (N/3)+1 bits width at level ln.sub.2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2.sup.X+1.gtoreq. N. A final comparator stage based on exclusive OR gates and an OR gate(s) compares the X+1 signals representing the actual bit count with an equal number of binary encoded signals representing the then desired number M, M.ltoreq.N, and produces an error signal if the number of binary ones detected is not equal to M. A preferred embodiment implementation of the berger code generator circuits utilizes exclusive OR logical elements based on the CMOS technology transfer gate structure.

Claims7

Dependent claims

An M out of N code checker circuit apparatus for determining if number M bits, where M.ltoreq.N and where such number M as is received by said circuit as binary-encoded first signals, is equal in number to that number of binary ones as between N binary input second signals, said circuit apparatus comprising:

code generator stage means for receiving said N binary input second signals in a plurality of parts, and for producing for each of said plurality of parts binary-encoded third signals representing the number of binary ones contained between the input signals of each respective part;
adder stage means for gathering all said binary-encoded third signals as are produced by said code generator means for each respective one of said plurality of parts, from said code generator stage means and for adding said binary-encoded third signals in order to produce as binary-encoded fourth signals that total binary ones bit count as is contained between said N binary input second signals;
and
comparator stage means for receiving said binary-encoded fourth signals which represent the total binary ones bit count from said adder stage means, and for receiving said binary-encoded first signals which represent the number M, and for producing an error signal if said binary-encoded fourth signals and said binary-encoded first signals are not equal;
whereby said error signal results if said total binary ones bit count between said N binary input signals was not equal in number to M;
whereby said circuit apparatus thusly checks an M out of N code between said N binary input signals for any number M.ltoreq.N.

3 more elements

Dependencies are inferred from the claim text.