Fast packet switching system

A fast packet switching system for switching plural bit signal packets of a plurality of messages from a plurality of digital transmission links comprises;

• a packet switching network comprising a plurality of interconnected packet switch nodes;
• a plurality of distributed controllers each for interfacingly connecting an individual one of said transmission links to one of said packet switch nodes and comprising;
• memory means for storing translation information for controlling the routing of packets of one of said messages communicated over said one of said links through a subset of said switch nodes to another of said controllers;
• and
• means for concatenating translation information stored in said memory means with packets of one of said messages to produce a plurality of address bits,
• said one of said switch nodes comprising:
• a plurality of output conductors for transmission of packets
• buffer means for variably storing bit signals of said received packet;
• and
• means controlled by said address bits responsive to a receipt of a packet communication available signal from another one of said switching nodes for designating one of said output conductors to route the then and subsequently stored bit signals of said received packet further through said network to said other one of said switching nodes.

A packet switching system for switching packets for a plurality of messages from a plurality of digital transmission links comprising:

• a packet switching network having a plurality of interconnected switching nodes;
• a plurality of distributed controllers each for interfacingly connecting an individual one of said transmission links to one of said switching nodes;
• processor means responsive to a receipt of one of said packets for one of said messages on a calling one of said controllers for generating translation information for routing other of said packets of said one of said messages through said network to a called one of said controllers;
• processor controller for forming a first control packet for communicating the generated translation information to said calling one of said controllers via said network;
• memory means in said calling one of said controllers responsive to said first control packet for storing translation information generated by said processor means for controlling the routing of said other packets of said one of said messages through said switching network to said called one of said controllers;
• and
• said processor means comprises validity checking means for effecting a reading of the translation information stored in said memory means of said calling one of said controllers by transmission of a second control packet via said network.

A fast packet switching system for switching packets for a plurality of messages from a plurality of digital transmission links comprising:

• a packet switching network having a plurality of interconnected packet switch nodes,
• a plurality of distributed controllers each for interfacingly connecting an individual one of said transmission links to one of said packet switch nodes and comprising,
• memory means for storing translation information for controlling the routing of packets of one of said messages communicated over said one of said links through a plurality of said switch nodes to another of said controllers, and
• means for concatenating translation information stored in said memory means with said packets of said one of said messages to produce a plurality of address bits, and
• said one of said switch nodes comprising
• a plurality of input conductors,
• a plurality of output conductors,
• means responsive to a packet communication available signal and a predetermined number of said plurality of address bits from one of said input conductors for routing a received packet of said one of said messages from said one of said input conductors to one of said output conductors defined by said predetermined number of address bits, and
• said one of said defined output conductors connected to another of said switching nodes which comprises
• buffer means for variably storing bit signals of said packets;
• means responsive to said buffer means of said other node having present capacity to partially receive one of said packets for transmitting said packet communications available signal;
• and
• means for repositioning said predetermined number of address bits in said plurality of address bits in the routing of said received packet to said defined one of said output conductors.

A packet switching system for communicating a message comprising a plurality of information packets and a call set-up packet, each of said information packets comprising logical address data, said system comprising:

• processor means responsive to a receipt of said call set-up packet for generating another logical address and physical address translation information;
• switching network means for switching said information packets to a destination;
• distributed controller means for communicating said information packets to said network means and comprising
• means for storing the other logical address and physical address translation information generated by said processor means;
• means responsive to a receipt of one of said information packets for inserting the other logical address into said one of said information packets;
• and
• means responsive to a receipt of one of said information packets for concatenating the stored physical address information in said storing means with said one of said information packets.

A packet switching system for the transmission of packets with each of said packets comprising a logical address field, a data field and flag fields, said switching system comprises

• customer terminals interconnected by switching networks;
• transmission facilities for communicating packets from said customer terminals;
• interface facilities connecting said transmission facilities to said networks;
• one of said interface facilities comprises
• means responsive to said logical address in a received one of said packets to transform said logical addresses to a network address for transmission of said received one of said packets through a connected network;
• and
• means responsive to said received one of said packets to send a request signal to said connected network;
• said connected network being responsive to said request signal to transmit an enable signal to said one of said interface facilities upon said connected network having present storage capacity to start the storage of said received one of said packets;
• said connected network being responsive to said network address to route said received one of said packets to another one of said interface facilities;
• and
• one of said customer terminals upon receiving said one of said packets performing the error recovery if an error resulted in transmission through said packet system.

A packet switching system comprising a switching network terminating a plurality of interface facilities interfacing said network with packet switching communication links;

• said network comprising a plurality of switching nodes;
• one of said interface facilities comprising means responsive to a receipt of a packet comprising a plurality of bits at a first predetermined rate for storing the entire packet and means responsive to a receipt of a transmission available signal from said network for transmitting the stored packet to one of said switching nodes at a second predetermined rate;
• and
• said one of said switching nodes comprising a variable buffering means for storing said bits of said received packet and means responsive upon the receipt of a transmission enable signal from a downstream one of said switching nodes for bypassing said buffering means immediately to effect the transmission of the stored bits of said received packet to said downstream one of said switching nodes.

A packet switching for the transmission of packets for customer terminals with flow control and error recovery functions performed by the originating and destination ones of said customer terminals, each of said packets comprising a logical address field, a data field and flag fields, said switching system comprises:

• switching networks;
• high speed transmission facilities;
• interface facilities connecting said transmission facilities to said networks;
• and
• each of said interface facilities comprising means for receiving said packets at a first predetermined rate and means for retransmitting said received packets at a second predetermined rate higher than said first predetermined rate to said connected network;
• one of said interface facilities responsive to the logical address field of one of said packets for forming a switch packet comprising a plurality of address bits and said one of said packets;
• said connected network comprises a plurality of interconnected packet switch nodes with one of said switch nodes interconnected to one of said interface facilities and comprising a plurality of output conductors,
• storage means for variably storing one of said packets and said plurality of address bits received from said one of said interface facilities;
• means responsive to a predetermined number of said plurality of address bits from said one of said interface facilities and a packet communication available signal from one of said output conductors defined by said predetermined number of address bits for immediately routing said received packet both from said variable storing means and from said one of said interface facilities to said one of said output conductors.

A packet switching system for communicating a message comprising a plurality of information packets and a call set-up packet, each of said information packets comprising logical address data, said system comprising:

• processor means responsive to a receipt of said call set-up packet for generating another logical address and physical address translation information;
• switching network means for switching said information packets to a destination;
• plurality of distributed controller means for bidirectionally communicating received information packets to said network means and each of said distributed controller means comprising
• means for storing the other logical address and physical address translation information generated by said processor means;
• means for inserting said other logical address into one of said information packets;
• and
• means responsive to a receipt of said one of said information packets for concatenating the stored physical address information in said storing means with said one of said information packets.

A fast packet switching system for switching packets for a plurality of messages from a plurality of digital transmission links comprising:

• a packet switching network having a plurality of interconnected packet switch nodes,
• one of said switch nodes comprising
• a plurality of input conductors,
• a plurality of output conductors,
• storage means for variably storing a packet of said one of said messages and a plurality of address bits received from one of said input conductors,
• means responsive to a predetermined number of said plurality of address bits from said one of said input conductors and a packet communication available signal from one of said output conductors defined by said predetermined number of address bits for immediately routing said received packet of said one of said messages to said one of said output conductors, and
• means for repositioning said predetermined number of address bits in said plurality of address bits in the routing of said received packet to said defined one of said output conductors.

A method of communicating packets through a packet switching system comprising switching networks interconnected by a plurality of high speed digital transmission means with each transmission means being connected to a given network by one of a plurality of interface facilities, first type packets comprising logical addresses are transmitted via said transmission means at first predetermined data rate and second type packets comprising network addresses are transmitted within said networks at a second predetermined data rate greater than said first predetermined data rate, each of said switching network comprising switching elements responsive to the network addresses of said second type packets to route said second type packets to destination ones of said interface facilities, said method comprising the steps:

• storing a one of said first type packets upon a receipt of said one of said first type packets by one of said interface facilities from associated transmission means;
• translating the logical address contained in said one of said first type packets to the corresponding network address and another logical address in response to the storage of said one of said first type packets;
• replacing said logical address with said other logical address in said one of said first type packets;
• assembling one of said second type packets by concatenating said network address and said one of said first type packets;
• and
• transmitting at said second predetermined data rate said one of said second type packets to said destination interface facility via said network.

A method of switching packets through a packet switching network comprising a first and a second stage with each stage being comprised of switching elements, each switching element having a plurality of input and output terminals, each of said switching elements of said first stage has an individual one of said output terminals connected to each of said switching elements of said second stage via the input terminals of said switching elements of said second stage, each switching element of said first and second stages having a variable storage means for buffering packets, said switching elements are responsive to an address contained within packets to route the packets from the input terminals to the address designated output terminals, and comprises the steps of

• variably storing the first portion of a packet received on the input terminal of one of said switching elements of said first stage;
• decoding said address field of said packet;
• rearranging said address for decoding by a sequential one of said switching elements;
• transmitting upon receipt of a link open signal said portion of said packet to the connected input terminal of a switching element of said second stage via the output terminal of said one of said switching elements of said first stage designated by said address field of said packet;
• and
• transmitting said link open signal upon the storage means associated with said connected input terminal having capability of partially receiving said packet from said switching element of said first stage.