US 4,494,114 AGranted

Security arrangement for and method of rendering microprocessor-controlled electronic equipment inoperative after occurrence of disabling event

AssigneeInternational Electronic Technology Corp.

InventorNorman Kaish

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Abstract

A lock-out security arrangement for and method of maintaining microprocessor-controlled electronic equipment normally operational until the occurrence of a disabling event, such as physical removal of the equipment from its normal installation, and/or electrical removal of the equipment from a source of electrical power, and thereupon for disabling the equipment after detecting the disabling event and for maintaining the equipment disabled, even after the disabling event has been discontinued, until a code manually entered via a keyboard associated with a microprocessor for controlling the normal operation of the equipment matches a private access code whose identity is protected from external interrogation by reason of being stored in an internal non-volatile memory of the microprocessor. The private access code is preferably selected by and known only to the user, and may be changed to a different private access code at the user's option.

Claims31

Dependent claims

A lock-out security arrangment for rendering electronic equipment having a normal operation inoperative after a disabling event has occurred, and for maintaining the equipment inoperative after the disabling event has terminated, comprising:

(a) a microprocessor having an internal, non-volatile, protected memory accessed solely by the microprocessor and protected from interrogation external to the microprocessor, said microprocessor being operative for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment;
(b) said security routine having means for distinguishing between an initial execution of the security routine and a subsequent execution of the security routine;
(c) means responsive to the initial execution of the security routine, for storing a first code in a secured manner in the internal memory of the microprocessor such that the stored first code is protected from interrogation external to the microprocessor;
(d) code entry means operatively connected to the microprocessor, for entering a second code to the microprocessor;
(e) said security routine having code validity means for comparing the second code entered using the code entry means to the stored first code whose identity is protected from external interrogation;
(f) enabling means responsive to a completed initial execution, or to the subsequent execution, of the security routine, for enabling the microprocessor to execute the operational routine after the first code has been stored in the internal memory of the microprocessor, and for maintaining the equipment normally operational until the disabling event has occurred;
(g) detector means operatively connected to the microprocessor, for detecting when the disabling event has occurred;
and
(h) disabling means responsive to the detector means and operatively connected to the microprocessor, for disabling the equipment from normal operation after the disabling event has occurred, said disabling means being further operative for maintaining the equipment disabled, even after the disabling even has terminated, until the second code matches the stored first code.

6 more elements

A lock-out security arrangement for rendering electronic equipment having a normal operation inoperative after a disabling event has occurred, and for maintaining the equipment inoperative after the disabling event has terminated, comprising:

(a) a microprocessor having an internal, non-volatile, protected memory accessed solely by the microprocessor and protected from interrogation external to the microprocessor, said microprocessor being operative for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment;
(b) said security routine having means for distinguishing between an initial execution of the security routine and a subsequent execution of the security routine;
(c) means responsive to the initial execution of the security routine, for storing a public code in the internal memory of the microprocessor;
(d) means for substituting a private code for the public code in a secured manner in the internal memory of the microprocessor such that the stored private code is protected from interrogation external to the microprocessor;
(e) code entry means operatively connected to the microprocessor, for entering a trial code to the microprocessor;
(f) said security routine having code validity means for comparing the trial code entered using the code entry means to the stored private code whose identity is protected from external interrogation;
(g) enabling means responsive to a completed initial execution, or to the subsequent execution, of the security routine, for enabling the microprocessor to execute the operational routine after the private code has been stored in the internal memory of the microprocessor, and for maintaining the equipment normally operational until the disabling event has occurred;
(h) detector means operatively connected to the microprocessor, for detecting when the disabling event has occurred;
and
(i) disabling means responsive to the detector means and operatively connected to the microprocessor, for disabling the equipment from normal operation after the disabling event has occurred, said disabling means being further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored private code.

7 more elements

(a) a microprocessor having an internal, non-volatile, protected memory accessed solely by the microprocessor and protected from interrogation external to the microprocessor, said microprocessor being operative for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment;
(b) said security routine having means for distinguishing between an initial execution of the security routine and a subsequent execution of the security routine;
(c) means responsive to the initial execution of the security routine, for storing a public code in the internal memory of the microprocessor;
(d) means for substituting a first private code for the public code in a secured manner in the internal memory of the microprocessor such that the stored first private code is protected from interrogation external to the microprocessor;
(e) code entry means operatively connected to the microprocessor, for entering a trial code to the microprocessor;
(f) said security routine having code validity means for comparing the trial code entered using the code entry means to the stored first private code whose identity is protected from external interrogation;
(g) enabling means responsive to a completed initial execution, or to the subsequent execution, of the security routine, for enabling the microprocessor to execute the operational routine after the first private code has been stored in the internal memory of the microprocessor, and for maintaining the equipment normally operational until the disabling event has occurred;
(h) detector means operatively connected to the microprocessor, for detecting when the disabling event has occurred;
(i) disabling means responsive to the detector means and operatively connected to the microprocessor, for disabling the equipment from normal operation after the disabling event has occurred, said disabling means being further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored first private code;
(j) means for changing the first private code to a second private code known only to an authorized user having knowledge of the first private code, and for storing the second private code in a secured manner in the internal memory of the microprocessor such that the stored second private code is protected from interrogation external to the microprocessor;
(k) said code validity means being further operative, after the second private code has been stored, for comparing the trial code entered using the code entry means to the stored second private code whose identity is protected from external interrogation;
and
(l) said disabling means being still further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored second private code.

10 more elements

A method of rendering electronic equipment having a normal operation inoperative after a disabling event has occurred, and for maintaining the equipment inoperative after the disabling event has occurred, comprising the steps of:

(a) programming a microprocessor having an internal, non-volatile, protected memory for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment;
(b) accessing the internal memory of the microprocessor solely by the microprocessor, and protecting the internal memory from interrogation external to the microprocessor;
(c) distinguishing between an initial execution of the security routine and a subsequent execution of the security routine;
(d) storing in response to the initial execution of the security routine a first code in a secured manner in the internal memory of the microprocessor such that the stored first code is protected from interrogation external to the microprocessor;
(e) entering a second code to the microprocessor;
(f) comparing the entered second code to the stored first code whose identity is protected from external interrogation;
(g) enabling the microprocessor in response to a completed initial execution, or to the subsequent execution, of the security routine, to execute the operational routine after the first code has been stored in the internal memory of the microprocessor, and maintaining the equipment normally operational until the disabling event has occurred;
(h) detecting when the disabling event has occurred;
(i) disabling the equipment from normal operation after the disabling event has occurred;
and
(j) maintaining the equipment disabled, even after the disabling event has terminated, until the entered second code matches the stored first code.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/558,115Filed 5 Dec 1983
Granted: 15 Jan 1985
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G08B 13/1418
For removal detection of electrical appliances by detecting their physical disconnection from an electrical system, e.g. using a switch…: removal…
G06F 21/31
Authentication, i.e. establishing the identity or authorisation of security principals: user authentication
G06F 21/88
Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer:…
G07C 9/33
In combination with an identity check: by means of a password