US 4,491,945 A · Fast packet switch

Abstract

A communication method and packet switching system in which packets comprising logical addresses and voice/data information are communicated through the system by packet switching networks which are interconnected by high-speed digital trunks with each of the latter being directly terminated on both ends by trunk controllers. During initial call setup of a particular call, central processors associated with each network in the desired route store the necessary logical to physical address information in the controllers which perform all logical to physical address translations on packets of the call. Each network comprises stages of switching nodes which are responsive to the physical address associated with a packet by a controller to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols. Each packet has a field which is automatically updated by the controllers for accumulating the total time delay incurred by the packet in progressing through the networks. Each processor has the capability of doing fault detection and isolation on the associated network, trunks, and controllers by the transmission of a single test packet. The testing is done solely in response to the test packet and no preconditioning of controllers or networks is necessary.

Claims57

Dependent claims

A packet switch comprising

a plurality of input conductors,
a plurality of output conductors,
means responsive to a predetermined group of a plurality of address bits in a packet of information bits from one of said input conductors for routing said packet of information bits to one of said output conductors defined by said predetermined number of address bits, and
means for repositioning said predetermined number of address bits in said plurality of address bits in the routing of said packet to said defined one of said output conductors.

1 more element

A packet switch for switching packets of digital signals between a plurality of input terminals and a plurality of output terminals, and said switch comprising:

a plurality of input control means each of which is connected to an individual one of said input terminals,
a plurality of output control means each of which is connected to an individual one of said output terminals,
means individually connecting each of said input control means to each of said output control means,
each of said packets comprising an address field of said digital bit signals defining a packet communication path from an individual one of said input control means over said connecting means and an individual one of said output control means to said individual one of said output terminals connected thereto, and
means for repositioning said digital bit signals of said address field of each packet received from said individual one of said input terminals in a routing of said received packet over defined packet communication path.

2 more elements

A packet switch for switching packets of digital signals between a plurality of input terminals and a plurality of output terminals, and said switch comprising:

a plurality of input control means each of which is connected to an individual one of said input terminals,
a plurality of output control means each of which is connected to an individual one of said output terminals,
means individually connecting each of said input control means to each of said output control means,
each of said packets comprising an address field of said digital signals defining a packet communication path from an individual one of said input control means over said connecting means and an individual one of said output control means to said individual one of said output terminals connected thereto,
the defined one of said input control means comprising controller means responsive to a receipt of said address field signals for sending a packet communication request signal over said connecting means to said individual one of said output control means,
the defined one of said output control means comprising control circuitry for supplying a signal over said connecting means to each of said input control means to signify the packet communication availabilty of said output control means and said individual one of said output terminals connected thereto, and
means in said each input and output control means responsive to tne supplied availability and request signals for communicating digital signals of a received packet over the defined packet communication path from said defined one of said input control means over said connecting means and defined one of said output control means to the defined one of said output terminals connected thereto.

4 more elements

A packet switching network comprising first and second switching stages each having a plurality of switching elements,

each of said elements comprising a plurality of input and output terminals,
each of said input terminals of said first stage being connectable to an individual input conductor,
means connecting each of said output terminals of said first stage to an individual one of said input terminals of said second stage,
each of said output terminals of said second stage being connectable to an individual output conductor,
each of said elements further comprising for each one of said input terminals thereof:
means for storing address and other digital signals of a packet received on said each one of said input terminals;
controller means for controlling said storing means to commence a transmission therefrom of said address and other digital signals of said packet upon a receipt of a control signal indicating an idle condition of the one of said output terminals identified by the stored address signals of said packet in said storing means;
means responsive to a storage of a ready signal in said storing means for supplying an idle condition indicating signal to said each one of said input terminals;
said supplying means comprises logic means operable for supplying said idle condition indicating signal to said each one of said input terminals and
further comprising for each one of said input terminals length register means for registering the length of a received packet in response to packet length digital signals storage in said storing means, and
said controller means being controlled by said registered packet length signals in said registering means for operating said logic means.

8 more elements

A packet switch for switching packets of digital signals from an input conductor to a plurality of output conductors and said switch comprising:

an input control means connected to said input conductor,
a plurality of output control means each of which is connected to an individual one of said output conductors,
means individually connecting said input control means to each of said output control means,
said input control means comprising controller means responsive to a receipt of address digital signals of a packet over said input conductor for sending a packet communication request signal over said connecting means to an individual one of said output control means defined by said address digital signals, and
said defined output control means comprising control circuitry responsive to said request signal and to a control signal on said output conductor connected to said defined output control means for sending a packet communication available signal over said connecting means to said input control means.

2 more elements

A method of switching packets through a packet switching network comprising a first and a second stage with each stage being comprised of switching elements, each switching element having a plurality of input and output terminals, each of said switching elements of said first stage has an individual one of said output terminals connected to each of said switching elements of said second stage via the input terminals of said switching elements of said second stage, each switching element of said first and second stages having a storage means for variably buffering packets, said switching elements are responsive to an address contained within packets to route the packets from the input terminals to the address designated output terminals, and comprises the steps of

storing the first portion of a packet received on the input terminal of one of said switching elements of said first stage;
decoding said address field of said packet;
and
transmitting said portion of said packet to the connected input terminal of a switching element of said second stage via the output terminal of said one of said switching elements of said first stage designated by said address field of said packet.

1 more element

A method of switching packets of digital signals between a plurality of input terminals and a plurality of output terminals via a switch comprising a plurality of input control means each of which is connected to an individual one of said input terminals, a plurality of output control means each of which is connected to an individual one of said output terminals, means individually connecting each of said input control means to each of said output control means, and each of said packets comprising an address field defining the communication path from an individual one of said input control means over said connecting means and individual one of said output control means to said individual one of said output terminals connected thereto and another plurality of input terminals, another plurality of output terminals, another plurality of input control means and another plurality of output control means, each output terminal of said stage connected to an individual one of said input terminals of said other stage, and each of said input control means of said stage and said other stage having an associated buffer for variably storing said packets, and comprises the steps:

transmitting a request signal over said individual connecting means to said designated individual one of said output control means in response to the receipt of said address field;
transmitting a grant signal to said receiving one of said input control means by said designated output control means in response to said request signal to signify the packet communication availability of said output control means and said individual one of said output terminals connected thereto;
transmitting the received packet to said output control means by said input control means in response to said grant signal;
transmitting a link open signal to said connected output terminal of said stage by one of said input terminals of said other stage upon said associated buffer of said one of said input control means of said other stage being capable of receiving a portion of a packet;
and
transmitting said grant signal to said connected input control means by said connected output control means of said stage upon receipt of said link open signal from said input control means of said other stage and said request signal from said connected input control means of said stage.

3 more elements

Dependencies are inferred from the claim text.

Fast packet switch

Life of this patent

Fast packet switch

Life of this patent

Abstract

Claims57