Frequency divider making use of Josephson junction circuits
AssigneeNippon Electric Co., Ltd.
InventorJunichi Sone
Life of this patent
Estimating the term…
Loading patent…
AssigneeNippon Electric Co., Ltd.
InventorJunichi Sone
Estimating the term…
A frequency divider is provided by coupling the gate current paths of a pair of Josephson junction gate circuits in parallel with the control current path of a third Josephson junction gate circuit being connected in series with the gate current path of one of the first pair of Josephson junctions. The gate current path of the third Josephson junction is connected in series with the control current path of the other of the first pair of Josephson junctions, and an input signal to be frequency divided is connected in common to the connection point of the control current path of the first Josephson junction and gate current path of the third Josephson junction. Current flowing through the control current path of the first Josephson junction will be at one-half the frequency of the input current. A plurality of frequency dividers may be cascaded to perform 1/2.sup.N frequency division.
A frequency divider circuit having a first frequency divider comprising first, second and thrid gate circuits each including a Josephson junction having a gate current path and a control current path, each said Josephson junction, in response to a control current flowing in its control current path, assuming a voltage state in which it presents an impedance to current flowing in its gate current path, and in response to the absence of said control current flowing in said control current path, assuming a zero voltage state in which it presents substantially no impedance to current flowing in its gate current path, the gate current paths of said first and second gate circuits being connected in parallel to each other between first and second parallel connection junctions, the control current path of said third gate circuit being connected between one of said parallel connection junctions and the gate current path of said first gate circuit, a first terminal adapted to be fed with a D.C. current having a sufficient magnitude for bringing said third gate circuit into the voltage state being connected to said one of said parallel connection junctions, a first resistor having a predetermined resistance and connected in series with the control current path of said first gate circuit to form a first series connection, said gate current path of said third gate circuit and control current path of said second gate circuit being connected in series to form a second series connection, and an input terminal receiving an input pulse signal to be frequency divided connected in common to said first and second series connections.
A switching circuit comprising first, second and third Josephson junction gate circuits each including a control current path and a gate current path which presents either one of a voltage state and a zero voltage state in response to a control current flowing through the associated control current path, each said Josephson junction gate circuit in its voltage state presenting an impedance to current flow through its gate current path and in its zero voltage state presenting substantially no impedance to current flowing through its gate current path, a D.C. current terminal, an input current terminal, a first current path including the gate current path of said first Josephson junction gate circuit and the control current path of said second Josephson junction gate circuit, a second current path including the gate current path of said third Josephson junction gate circuit, a third current path including the control current path of said first Josephson junction gate circuit, a fourth current path including the gate current path of said second Josephson junction gate circuit and the control current path of said third Josephson junction gate circuit, means for providing a D.C. current through either one of said first and second current paths via said D.C. current terminal, and means for providing an input current through either one of said third and fourth current paths via said input current terminal.
Dependencies are inferred from the claim text.