Freeze clock circuit
AssigneeRCA Corporation
InventorsJoseph P. Paradise, Donald J. Derkach
Life of this patent
Estimating the term…
Abstract
A circuit for controlling the application of a timing pulse to a count down chain where the contents of the count down chain are read-out in stages and asynchronously with respect to the application of the timing pulse. The control circuit ensures that a timing pulse is not applied during the read-out of the contents of the count down chain.
Claims8
A timing system comprising:
- a plurality of counters, each counter having a toggle input to which is applied a counting pulse and having an output;
- read-out means coupled to said counters responsive to a read-out command for selectively reading-out their contents;
- a source of regularly occurring input pulses;
- and
- control means coupling said source of regularly occuring input pulses to the toggle input of at least one of said plurality of counters for normally applying said input pulses with little, if any, delay to the input of said at least one of said plurality of counters, said control means including means for generating a timing signal for a period of time T1 prior to each occurrence of said regularly occurring input pulses, said control means being responsive to said timing signal and to the occurrence of a read-out command within said given time period, T1, for delaying the application of said input pulse for a period of time T2 which is sufficiently long to enable the read-out of said plurality of counters one at a time, and said control means including means for applying a delayed input signal to the toggle input of said at least one of said plurality of counters following said period of time T2.
In combination with a real time clock comprised of an oscillator producing regularly occurring timing signals applied to a count down chain and including reading means coupled to the count down chain producing read signals for selectively reading the contents of the count down chain in sections and asynchronously with respect to said timing signals whereby an erroneous read-out of the contents of the count down chain can occurr as a result of a timing signal being generated during a read-out of the contents of the count down chain, the improvement comprising:
- control means coupled between said oscillator and said count down chain normally coupling said regularly occurring timing signals to said count down chain with substantially no delay, and
- said control means including means responsive to signals from said oscillator for producing a time slot a given time T1 before the occurrence of each one of said regularly occurring timing signals and said control means being responsive to the occurrence of said read signal during said time slot for delaying the application of said regularly occurring timing signal to the count down chain for a second period of time T2 which is sufficiently long to enable the read-out of all the sections of said count down chain.
Dependencies are inferred from the claim text.