Two dimensional press brake control system and apparatus

A press brake controller for producing a control signal to control the ram of a press brake, said press brake controller enabling said press brake to repetitively perform a bend having a predetermined dimension value corresponding to a bend angle, each bend being initiated according to a ram control switch, said controller including:

• means for providing an averaged ram position signal corresponding to said predetermined dimension value;
• a ram encoder connected to said ram providing a ram location signal;
• a ram signal comparator forming a ram error signal corresponding to the difference between each said location signal and said ram position signal;
• a ram error averager receiving said ram error signal and forming a ram average error signal corresponding to the average of a plurality of each said ram error signals, said plurality of ram error signals including ram error signals from a prior bend;
• and
• a ram signal compensator forming a control signal corresponding to the sum of said ram position signal and said ram average error signal.

Means for data communication between a first processor system and a second processor system comprising:

• a communication channel interconnecting said first and second processor systems;
• message transmission means within said first processor system for providing a message signal to said transmission channel;
• message echo means within said second processor system for subsequently retransmitting said message signal on said transmission channel from the received said message signal;
• means to compare the message signal retransmitted by the second processor system with the message signal transmitted by the first processor system;
• message verify means within said first processor system for subsequently providing a verify signal on said communication channel upon correct receipt of said message signal after retransmission on said transmission line;
• verify echo means within said second processor system for subsequently retransmitting said verify signal on said communication channel as received by said verify echo means;
• and
• means to indicate the equality of the message and the message echo signals, and the message verify and the echo verify signals.

A method of data communication between a first processor and a second processor system comprising the steps of:

• sending a message signal from the first processor to be received by the second processor;
• sending a message echo from the second processor to be received by the first processor;
• comparing the message echo received by the first processor with the message signal sent by the first processor;
• sending a verify signal from the first processor to be received by the second processor;
• sending a verify echo signal from said second processor to be received by the first processor;
• and
• indicating the receipt of said verify echo signal, wherein the message signal is retransmitted if the message echo signal differs from the message signal, and said verify signal is retransmitted if the verify echo signal does not correspond thereto.

A digital multiplier receiving sine and cosine incremented encoders signals, each said sine and cosine signal having a periodicity, said multiplier comprising:

• direction detection means for producing a direction output signal;
• transition detection means for receiving said sine and cosine signals producing a rate output signal having a periodicity at a multiple of said sine and cosine signal periodicity;
• clock means for providing periodic clock pulses;
• and
• inhibit means for detecting a first transition of said sine and cosine signals after said clock pulse, wherein said inhibit means operates for inhibiting said transition detection when said sine and cosine signals make a transition before the subsequent clock pulse.

A digital multiplier receiving sine and cosine incremental encoders signals, each said sine and cosine signal having a periodicity, said multiplier comprising:

• direction detection means for receiving said sine and cosine signals and for producing a direction output;
• transition detection means for receiving said sine and cosine signals and for producing a rate output signal having a periodicity at a multiple of said sine and cosine signal periodicity;
• clock means for providing periodic clock pulses;
• and
• inhibit means to inhibit said rate output signal when transitions from a first state to a second state to said first state occur within one of said clock periods.

A press brake controller for producing a control signal to control the travel of the ram of a press brake, said controller including:

• means for providing a specified ram position signal corresponding to a predetermined bend parameter;
• a ram encoder connected to said ram providing an actual ram position signal;
• a ram signal comparator forming a ram error signal corresponding to the difference between said ram location signal and said ram position signal;
• and
• a ram signal compensator forming said control signal corresponding to the averaged sum of said ram position signal and said ram error signal, wherein said ram encoder comprises:
• incremental encoder means connected to the press brake for providing sine and cosine pulse output pulse signals each having a pulse rate corresponding to the velocity of the attached press brake element motions;
• digital multiplier means including:
• direction detection means for producing a direction output;
• transition detection means for receiving said sine and cosine output signals and for producing a rate output at a multiple of said incremental encoder pulse rate;
• clock means for providing periodic clock pulses;
• and
• inhibit means for inhibiting said transition detection means rate output signal transition when one of said sine and cosine input signals has a duration of less than one clock pulse period, wherein said direction output and said rate output taken together form said ram position signal.

A press brake controller for producing a control signal to control the ram of a press brake, said press brake controller enabling said press brake to repetitively perform a bend having a predetermined dimension value corresponding to a bend angle, each bend being initiated according to a ram control switch, said controller including:

• a ram position specifier providing an averaged ram position signal corresponding to said predetermined dimension value;
• a ram encoder connected to said ram providing a ram location signal;
• a ram signal comparator forming a ram error signal corresponding to the difference between each said location signal and said ram position signal;
• a ram error averager receiving said ram error signal and forming a ram average error signal corresponding to the average of a plurality of each said ram error signals, said plurality of ram error signals including ram error signals from a prior bend;
• and
• a ram signal compensator forming a control signal corresponding to the sum of said ram position signal and said ram average error signal, wherein said ram encoder comprises:
• incremental encoder means connected to the press brake providing sine and cosine pulse output pulse signals each having a pulse rate corresponding to the velocity of the attached press brake element motions;
• digital multiplier means including:
• direction detection means producing a direction output;
• transition detection means receiving said sine and cosine output signal producing a rate output at a multiple of said incremental encoder pulse rate;
• clock means providing periodic clock pulses;
• and
• inhibit means to inhibit said transition detection means rate output signal transition when one of said sine and cosine input signals has a duration of less than one clock pulse period, wherein said direction output and said transition rate output taken together form said ram position signal.