US 4,486,826 AGranted

Computer peripheral control apparatus

AssigneeStratus Computer, Inc.

InventorsKenneth T. Wolff, Joseph E. Samson, Kurt F. Baty

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Abstract

A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Claims9

Dependent claims

Peripheral control apparatus for connection with a computer bus structure for the transfer of data between one or more computer functional units connected to that bus structure and at least one computer peripheral device connected with the control apparatus, where each functional unit is any of a central processing unit, a memory unit, and another peripheral control unit, and where the bus structure includes first and second duplicative buses, said apparatus having the improvement comprising

A. input means for receiving signals from any of said other functional units by way of any of said first and second buses and being conditioned by an applied control signal input thereto from said bus structure for responding to such signals on only a single one of said first and second buses,
B. bus output means for applying signals, for transfer to any of said other functional units, identically to both of said first and second buses independent of the conditioning of said input means,
C. device output means for connection to the peripheral device,
D. first and second device control means, each of which is connected with said input means to receive signals from said bus structure and is arranged for providing identical operations in response to said received signals and for producing output signals in response to said operations, and at least said first of which is arranged to apply output signals to said bus output means and to apply further output signals to said device output means, and
E. first fault-detecting means for detecting a first selected fault condition at least in signals transferred with respect to said device control means and responding to such a detected fault-condition to disable said bus output means from applying signals to either of said first and second buses.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/307,524Filed 1 Oct 1981
Granted: 4 Dec 1984
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 11/1625
Error detection by comparing the output signals of redundant hardware: in communications, e.g. transmission, interfaces
G06F 11/1641
Error detection by comparing the output of redundant processing systems: where the comparison is not performed by the redundant processing components
G06F 11/2007
Where interconnections or communication control functionality are redundant: using redundant communication media
G06F 13/374
With decentralised access control: using a self-select method with individual priority code comparator