Loading patent…
AssigneeInternational Business Machines Corporation
InventorsSe J. Hong, Ravindra K. Nair, Eugene Shapiro
Estimating the term…
Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array or processors may be utilized to wire a much larger array of cells.
In a system for determining wire routings between terminals on a master-slice chip, wherein a plurality of devices are formed on said chip, with a plurality of mutually orthogonal horizontal and vertical wiring channels formed on said chip, with a plurality of wiring tracks being formed in each channel, with said devices and channels forming an array of cells, with said terminals being placed along the wiring tracks in at least one of the horizontal and vertical wiring channels, the combination comprising:
A method of determining wire routings between terminals on a master-slice chip, wherein a plurality of devices are formed on said chip, with a plurality of mutually orthogonal horizontal and vertical wiring channels being formed on said chip, with a plurality of wiring tracks being formed in each channel, witn said devices and channels forming an array of cells, with said terminals being placed along the wiring tracks in at least one of the horizontal and vertical wiring channels, with a net being defined as a set of at least two terminals that have to be connected together, including an array of processing elements, equal in number to at least a submultiple of the number of cells formed on said chip, said processing elements including at least four input/output ports for communicating with at least the four adjacent neighbors in the array of processing elements, and including a control input/output port, with a control processor for selectively providing commands to said control input/output port of each said processing elements in said array of processing elements to concurrently determine the wire routings from a plurality of source terminals to a plurality of sink terminals, said method comprising the steps of:
A method of determining wire routings between terminals on a master-slice chip, wherein a plurality of devices are formed on said chip, with a plurality of mutually orthogonal horizontal and vertical wiring channels being formed on the chip, with a plurality of wiring tracks being formed in each channel, with said devices and channels forming an array cells, with said terminals being placed along the wiring tracks in at least one of the horizontal and vertical wiring channels, with a net being defined as a set of at least two terminals that have to be connected together, with port cost being defined as the penalty for occupying a given track in a given direction, including an array of processing elements, equal in number to at least a submultiple of the number of devices formed on said substrate, said processing elements each including at least four input/output ports for communicating with at least the four adjacent neighbors in the array of processing elements, and including a control input/output port, with a control processor for selectively providing commands to said control input/output port of each said processing elements in said array of processing elements to concurrently determine the wire routing from a plurality of source terminals to a plurality of sink terminals, said method comprising the steps of:
A method of determining wire routings between terminals on a master-slice chip, wherein a plurality of devices are formed on said chip, with a plurality of mutually orthogonal horizontal and vertical wiring channels being formed on the chip, with a plurality of wiring tracks being formed in each channel, with said devices and channels forming cells in an N by M array which may be divided into n by m frames, where n<N and m<M, with said terminals being placed along the wiring tracks in at least one of the horizontal and vertical wiring channels, with a net being defined as a set of at least two terminals that have to be connected together, with port cost being defined as the penalty for occupying a given track in a given direction, including an n by m array of processing elements, said processing elements including at least four input/output ports for communicating with at least the four adjacent neighbors in the array, and including a control input/output port, with a control processor for selectively providing commands to said control input/output port of each said processing elements in said array to concurrently determine the wire routing from a plurality of source terminals to a plurality of sink terminals, an n by m frame at a time, said method comprising the steps of:
Dependencies are inferred from the claim text.