US 4,480,307 AGranted

Interface for use between a memory and components of a module switching apparatus

AssigneeIntel Corporation

InventorsDavid L. Budde, David G. Carson, David B. Johnson, Doran K. Wilde

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Abstract

A number of intelligent bus interface units (100) are provided in a matrix of orthogonal lines interconnecting processor modules (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits. Write-request packets and read-request packets are issued to the memory-control unit. The memory-control unit responds with reply packets. A message controller (416), bus monitor (413), and pipeline and reply monitor ( 414), run the memory bus in a three-level pipeline mode. There may be three outstanding requests in the bus pipeline. Any further requests must wait for a reply message to free-up a slot in the pipeline before proceeding. Request messages increase the length of the pipeline and reply messages decrease the length of a pipeline. A control message, called a blurb, does not affect the pipeline length and can be issued when the pipeline is not full. The different messages are distinguished by three control signals (405) that parallel the data portion of the bus. The message generator (417) and interface logic (404) drive these control lines to indicate the message type, the start and end of the message, and possible error conditions. The pipeline and reply monitor (414) and the message controller (416) cooperate to insert a reply to a particular request in the pipeline position corresponding to the particular request that invoked the reply.

Claims8

Dependent claims

For use with a memory bus including a data portion, said bus providing the means of communication between a memory control unit connectable to a memory module capable of being accessed by said memory control unit, and at least one bus interface unit connectable to a data processor, said data processor being capable of issuing memory requests including address information for a data transfer operation requested of said memory and capable of receiving memory replies including data requested from said memory, each of said memory replies being responsive to a particular memory request, wherein accesses to said memory are handled by means of a series of messages transmitted to said memory control unit in accordance with a specific control protocol, said data processor being further capable of issuing control information for bus transactions, the combination comprising:

message generator means for generating messages in the form of packets of information for transmission on said memory bus, said messages being divided into message types including control message types of packets, request message types of packets corresponding to said memory requests, and reply message types of packets corresponding to said memory replies, each packet comprising one or more bus transmission slots issued by said message generator means sequentially and contiguously, each bus transmission slot in a packet being capable of including an opcode, address, data, control, and parity-check bits;
a pipeline queue;
message controller means connected to said message generator means and to said pipeline queue for controlling said request message packets and said reply message packets such that a predetermined number of said request message packets may be entered into said pipeline queue at any one time;
monitor means connected to said message controller means and to said memory bus for monitoring said request message packets and said reply message packets generated on said bus by said message generator, such that request message packets in excess of said predetermined number are prevented from being generated until a reply message packet is received to thereby free-up a slot in the pipeline;
control signal lines operative in parallel with the data portion of said bus for providing a coded signal representing a particular message type generated on said bus by said message generator;
and,
interface logic means connected to said message generator means and to said control signal lines, responsive to said message generator, for driving said control lines to indicate the message type;
said message generator means including means for inserting a particular reply message packet corresponding to a particular request message packet in said pipeline queue at a position in said pipeline queue corresponding to the request message packet that is associated with said particular reply message packet.

5 more elements

In a data processing system in which a switching matrix provides electrical interconnections between horizontal MACD buses and vertical ACD buses connected in said matrix by means of nodes including bus interface unit nodes and memory-control unit (MCU) nodes, communication means in one of said nodes comprising:

recognizing means connected to said ACD bus for recognizing signals on said ACD bus representative of a request to said one node;
means connected to said MACD bus, responsive to said recognizing means, for generating on said MACD bus, signals on said MACD bus representative of a write-request packet or a read-request packet, said packets comprising a number of bus transmission slots, issued sequentially and contiguously, each slot in a packet including opcode/address/data bits and control bits,
said write-request packet comprising an opcode specifying a function desired, an address specifying a physical memory location, and write data,
said read-request packet including an opcode specifying a function desired, and an address specifying a physical memory location;
receiving means connected to said MACD bus for receiving a reply message packet on said MACD bus, said reply message packet comprising a number of bus transmission slots, received sequentially and contiguously, each slot in said reply packet including opcode/data bits and control bits,
said reply message packet containing a header opcode and/or data;
message control means connected to said generating means and said receiving means, said message control means including:
means for queuing data in said write request packet, means responsive to said control bits in said read and write packets for detecting the start and end of a packet, means for decoding said opcode to perform a function desired,
means for establishing a pipeline for said request message packets and said reply message packets generated on said bus by said message generator, and,
monitor means connected to said message control means and to said MACD bus, for monitoring signals on said MACD bus representative of said request and reply packets on said bus, such that a request packet is prevented from entering said pipeline until a reply packet is received to free-up a slot in said pipeline, whereby request packets increase the length of said pipeline up to a predetermined number of request
packets in said pipeline, and reply packets decrease the length of said pipeline;
and,
means connected to said recognizing means, said generating means, said message control means, and said receiving means, for arbitrating said signals on said ACD bus representative of requests from said ACD bus going onto said MACD bus and said signals on said MACD bus representative of replies received from said MACD bus, to thereby enable said message control means to insert a reply packet associated with a particular request packet in the pipeline position of said recognized request packet.

10 more elements

Dependencies are inferred from the claim text.