Integrated circuit with interruptable oscillator circuit

A semiconductor integrated circuit capable of being set to an operation mode or a stand-by mode comprising:

• (a) oscillator means for providing a pulsed oscillation signal when an enable signal indicates that said semiconductor integrated circuit is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said semiconductor integrated circuit is in said stand-by mode;
• (b) timing generator means coupled to said oscillator means for generating, in response to said oscillation signal and a timing means enable signal, timing signals for a said semiconductor integrated circuit and for generating an oscillation block release signal in response to a first signal;
• (c) gate means coupled to said oscillator means and said timing generator means for outputting said enable signal, said gate means having one input receiving a second signal indicating the end of said stand-by mode and a second input receiving said oscillation block release signal from said timing generator means;
• and
• (d) counter means coupled to said oscillator means and said timing generator means for counting a predetermined number of pulses of said oscillation signal and for generating said timing means enable signal to allow said timing generator means to generate said timing signals.

An operational control system including a high integration density semiconductor element capable of being selectively set to an operation mode and a stand-by mode, said system comprising:

• (a) a memory for storing operational control instructions;
• (b) decoder means coupled to said memory for decoding said operational control instructions read from said memory and for producing control signals;
• (c) a data bus for providing data transfer;
• (d) an input/output port coupled to said data bus for inputting and outputting data on said bus;
• (e) arithmetic and logic means coupled to said data bus for performing arithmetic and logic operations on data appearing on said data bus;
• (f) oscillator means for generating an oscillation signal when an enable signal indicates that said operational control system is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said operational control system is in said stand-by mode;
• (g) timing generator means coupled to said oscillator means and said data bus generating, in response to said oscillation signal, timing signals for use by said operational control system and for generating an oscillation block signal in response to a first signal supplied via said data bus in response to one of said control signals;
• and
• (h) gate means coupled to said oscillator means and said timing generator means for outputting said enable signal, said gate means having one input receiving, from said input/output port, a second signal indicating the onset of said stand-by mode and a second input receiving said oscillation block signal from said timing generator means.

An operational control system including a high integration density semiconductor element capable of being selectively set to an operation mode and a stand-by mode, said system comprising:

• (a) a memory for storing operational control instructions;
• (b) decoder means coupled to said memory for decoding said operation control instructions read from said memory to produce control signals;
• (c) a data bus for data transfer;
• (d) an input/output port coupled to said data bus for inputting and outputting data on said bus;
• (e) arithmetic and logic unit means coupled to said data bus for performing arithmetic and logic operations on data appearing on said data bus;
• (f) oscillator means for generating a pulse oscillation signal when an enable signal indicates that said operational control system is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said operational control system is in said stand-by mode;
• (g) timing generator means coupled to said oscillator means for generating, in response to said oscillation signal and a timing generator enable signal, timing signals for said operational control system and for generating an oscillation block release signal in response to a first signal supplied via from said data bus in response to one of said control signals;
• (h) gate means coupled to said oscillator means, said input/output port, and said timing generator means, for outputting said enable signal, said gate means having one input receiving, from said input/output port, a second signal indicating the end of said stand-by mode and a second input receiving said oscillation block release signal from said timing generator means;
• and
• (i) counter means coupled to said oscillator means and said timing generator means for counting a predetermined number of pulses of said oscillation signal and then for generating a timing means enable signal to allow said timing generator means to generate said timing signals.