Semiconductor integrated circuit device including means for reducing the amount of potential variation on a reference voltage line

A semiconductor integrated circuit device comprising:

• a semiconductor substrate;
• a pair of first and second wiring layers that are formed on said semiconductor substrate and to which a power-supply voltage is applied;
• an electronic circuit connected between said first wiring layer and said second wiring layer, and to which said power-supply voltage is applied via said first and second wiring layers;
• a reference voltage generator which contains a plurality of resistance elements and which produces a reference voltage upon receipt of the power-supply voltage via said first and second wiring layers;
• a third wiring layer formed on said semiconductor substrate and to which said reference voltage is applied;
• an input circuit which is comprised of a plurality of insulated gate field effect transistors, and which has a first input terminal that receives input signals from the outside of said semiconductor substrate, and a second input terminal to which said reference voltage is applied via said third wiring layer;
• a first capacitor connected between said first wiring layer and said third wiring layer;
• and
• a second capacitor connected between said second wiring layer and said third wiring layer,
• wherein when first and second potential variations substantially equal in magnitude and opposite in phase have developed respectively on said first and second wiring layers due to changes in the operation current of said electronic circuit, the potential variation supplied to said third wiring layers via said first capacitor is substantially cancelled by the potential variation supplied to said third wiring layers via said second capacitor.