Cache buffered memory subsystem
AssigneeStorage Technology Corporation
InventorP. David Dodd
Life of this patent
Estimating the term…
Abstract
A buffered cache memory subsystem is disclosed which features a solid-state cache memory connected to a storage director which interfaces a host channel with a control module controlling operation of a long-term data storage device such as a disk drive. The solid-state cache memory is connected to plural directors which in turn may be connected to differing types of control modules, whereby the cache is usable with more than one type of long-term data storage means within a given system. The cache memory may be field-installed in a preexisting disk drive storage system and is software transparent to the host computer, while providing improvements in overall operating efficiency. In a preferred embodiment, data is only cached when it is expected to be the subject of a future host request.
Claims14
A data storage system for use with a host computer, said computer comprising an arithmetic and logic unit and a main memory unit for containment of data to be processed and of programs to control said processing, said host computer being adapted to generate input/output commands directed to secondary data storage means connected to said host computer via channel means, said secondary data storage means comprising:
- one or more long-term magnetic data storage means;
- control module means for controlling said long-term data storage means;
- director means for controlling flow of data between said channel means, said control module means and said longterm data storage means in response to an input/output command;
- and
- solid-state cache memory means for containment of data anticipated to be the subject of a subsequent input/output command, said cache memory means being connected to said director means by first circuit means establishing a first data path from said long-term data storage means through said control module means and said director means into said cache, and by second circuit means establishing a second data path from said cache through said director means to said channel means.
In a data storage and processing system comprising a host computer comprising an arithmetic and logic unit and a main memory means, and a long-term data storage system, said long-term data storage system being operatively connected to said host by channel means for transfer of data and control information therebetween, said long-term data storage means being adapted to respond to input/output commands generated by said host computer by controllable juxtaposition of read/write head means with respect to recording media, said juxtaposition being performed under control of control module means selected to control the particular read/write head means and recording media selected, and director means adapted to interface said control module means to said channel means, the improvement which comprises:
- cache memory means of faster access speed than said long-term data storage means and cache memory controller means being operatively connected by circuit means to said director means, said cache memory means being controlled by said controller for containment of data, and said controller means being adapted to provide an indication that such containment would be effective in increasing overall efficiency of utilization of said host.
Dependencies are inferred from the claim text.