Circuit for interfacing with both TTL and CMOS voltage levels

A circuit for providing an output signal within predetermined CMOS voltage levels in response to a voltage level selection signal having at least a predetermined value and within predetermined TTL voltage level inputs otherwise, comprising:

• input signal level detection means characterized by receiving said voltage level selection signal, and providing a CMOS mode control signal at a first output when said selection signal is equal to or greater than said predetermined value, and otherwise providing a TTL mode control signal at a second output;
• reference voltage means characterized by receiving said selection signal at a first input and having a second input coupled to the first output of said input signal level detection means, for providing a reference voltage which is referenced to the voltage of said selection signal at an output;
• and
• output buffer means having a first input coupled to the first output of said input signal level detection means, a second input coupled to the second output of said input signal level detection means, a third input coupled to the output of said reference voltage means, and a fourth input for receiving an input data signal, for providing an output signal having a logic level related to the input data signal, and having CMOS voltage levels in response to said CMOS mode control signal or TTL voltage levels in response to said TTL mode control signal.

A circuit for receiving a CMOS input signal in response to a select signal being within a first predetermined range, and for receiving a TTL input signal in response to the select signal being within a second predetermined range, wherein the first and second predetermined ranges are adjacent one another, comprising:

• input signal level detection means characterized by receiving said select signal, for detecting whether said select signal is in said first or said second predetermined range;
• reference voltage means coupled to said input signal level detection means and characterized by receiving said select signal, for providing a reference voltage which is referenced to said select signal;
• and
• input buffer means coupled to said input detection means and to said reference voltage means, for receiving an input signal having a CMOS voltage level in response to said select signal being within said first predetermined range, and for receiving an input signal having a CMOS voltage level in response to said select signal being within said adjacent second predetermined range, said input buffer means providing an output signal, in response to the input signal, having a logic level within a predetermined CMOS voltage range.

A circuit for providing a CMOS output signal in response to a select signal being within a first predetermined range, and for providing a TTL output signal in response to said select signal being within a second predeteremined range, wherein the first and second predetermined ranges are adjacent one another, comprising:

• input signal level detection means characterized by receiving said select signal, for detecting whether said select signal is in said first or said second predetermined range;
• reference voltage means coupled to said input signal level detection means and adapted to receive said select signal, for providing a reference voltage which is referenced to said select signal;
• and
• output buffer means coupled to said input signal level detection means and to said reference voltage means, for receiving an input data signal and providing a circuit output signal having a logic level related to the input data signal and having CMOS voltage levels in response to said select signal being within said first predetermined range, and TTL voltage levels in response to said select signal being within said adjacent second predetermined range.